Ques:- Why latches (other than lock-up and clock gating) in design are
bad for ATPG? We always loose coverage by putting them on transparent mode by
constraining enable signal. How can we increase this coverage?
Ans:- I think you answered your own question regarding why we lose
coverage,
"putting them on transparent mode by constraining enable signal".
Any logic driving the enable signal will lose some coverage due to this constraint.
If the enable signal is driven by a large cone of logic, you can increase the coverage by adding a "force transparent on" gate close to the enable of the latch, and add an observe flip-flop just before the added gate, so that most of the faults in the logic cone can be recovered.
Without modifying the circuitry, recovering fault coverage in ATPG really depends on how these latches are used in the functional path.
"putting them on transparent mode by constraining enable signal".
Any logic driving the enable signal will lose some coverage due to this constraint.
If the enable signal is driven by a large cone of logic, you can increase the coverage by adding a "force transparent on" gate close to the enable of the latch, and add an observe flip-flop just before the added gate, so that most of the faults in the logic cone can be recovered.
Without modifying the circuitry, recovering fault coverage in ATPG really depends on how these latches are used in the functional path.
Ques:-
when
both the Transition-delay and path_delay target for transition faults, why we
should have two different methods to detect the same?
Ans:- Transition
delay is similar to stuck-at atpg, except that it attempts to detect
slow-to-rise and slow-to-fall nodes, rather than stuck-at-0 and stuck-at-1
nodes. A slow-to-rise fault at a node means that a transition from 0 to 1 on
the node doesnot produce the correct results at the maximum operating speed of
the design. Similarly a slow-to-fall fault means that a transition form 1 to 0
on a node doesnot produce the correct results at the maximum speed of the
design.Transition delay fault targets single point defects.
The Path delay fault model is useful for testing and characterizing critical timing paths in the deisgn. Path delay fault tests exercise critical paths at-speed to detect whether the path is too slow because of manufacturing detects or variations.
Path delay fault testing targets physical defects that might affect distributed region of a chip. For example, incorrect field oxide thicknesses could lead to slower signal propogation times, which could cause transitions along a critical path to arrive too late.
The Path delay fault model is useful for testing and characterizing critical timing paths in the deisgn. Path delay fault tests exercise critical paths at-speed to detect whether the path is too slow because of manufacturing detects or variations.
Path delay fault testing targets physical defects that might affect distributed region of a chip. For example, incorrect field oxide thicknesses could lead to slower signal propogation times, which could cause transitions along a critical path to arrive too late.
Note:------------------
If we
attain 100% coverage with transition atpg test then we dont need to do the path
delay test.
But this is not the case in most of our designs. Then how can we GUARANTEE that all the critical paths are targeted by Transition ATPG
so we give the critical path to the atpg tool and tell it to generate patterns for it
this is called path delay
But this is not the case in most of our designs. Then how can we GUARANTEE that all the critical paths are targeted by Transition ATPG
so we give the critical path to the atpg tool and tell it to generate patterns for it
this is called path delay
Ques:- What
is Burn in test? Why is it done?
Ans:- Burn-in is
the process by which device infant mortality failures are
accelerated through application of temperature and stress voltages for
specific periods of time. The goal of burn-in is to stress the device as much
as possible thereby accelerating device infant mortality rate. Since scan
based test has higher coverage, scan test vectors are used to stress the logic
portion of the device. This can either be done by performing device level
ATPG by applying external test patterns on onchip LBIST. Memory BIST is
used for memories
Note :-----------------
accelerated through application of temperature and stress voltages for
specific periods of time. The goal of burn-in is to stress the device as much
as possible thereby accelerating device infant mortality rate. Since scan
based test has higher coverage, scan test vectors are used to stress the logic
portion of the device. This can either be done by performing device level
ATPG by applying external test patterns on onchip LBIST. Memory BIST is
used for memories
Note :-----------------
High toggled
atpg vectors are generated to sensitize the internal nodes of the chip so that
chip will get more stress
Ques:--
If for a DFT production set we have both PATH Delay and
Transition patterns which scheme should be done first ?
Ans:-
Its always better to do Path_delay first and then the transition
delay.
Path_delay- start flop and end flop are given by the user.(i.e) transition through a well defined path-(More effective)
Transition-Start and end flop is decided by the tool,so trasition may happen through a shorter or longer path-(Less effective)
1)path delay basically targets for all the critical paths in the design.
2)Generate the path_delay patterns for all the critical paths in the design and write down the faults for the same.
3) Generate the transition delay pattern by loading the faults on the path_delay, such that the faults detected in the path_delay are not Re-targeted.
4) The major reason to follow the above sequence is in trans-delay we are not sure weather a transition has really happened through the critical path.
(A)-If we do the transition-ATPG first, we are not sure whether the transition has happened through the critical path,In such case we may not have pattern which may catch the fault through the critical path,but the fault may be detected through some other shorter paths which may add the faults to the detected list.
(B)If we run a path_delay after the above step(A) then we may have a pattern for the critical path,but it leads to the pattern redundancy because we have already a transition pattern for the same fault.
Path_delay- start flop and end flop are given by the user.(i.e) transition through a well defined path-(More effective)
Transition-Start and end flop is decided by the tool,so trasition may happen through a shorter or longer path-(Less effective)
1)path delay basically targets for all the critical paths in the design.
2)Generate the path_delay patterns for all the critical paths in the design and write down the faults for the same.
3) Generate the transition delay pattern by loading the faults on the path_delay, such that the faults detected in the path_delay are not Re-targeted.
4) The major reason to follow the above sequence is in trans-delay we are not sure weather a transition has really happened through the critical path.
(A)-If we do the transition-ATPG first, we are not sure whether the transition has happened through the critical path,In such case we may not have pattern which may catch the fault through the critical path,but the fault may be detected through some other shorter paths which may add the faults to the detected list.
(B)If we run a path_delay after the above step(A) then we may have a pattern for the critical path,but it leads to the pattern redundancy because we have already a transition pattern for the same fault.
Ques:-- What is IDDQ Testing?
Ans:- IDDQ Testing can detect certain types of circuit faults in CMOS
circuits that are difficult or impossible to detect by other methods. IDDQ testing, when used with standard
functional or scan testing, provides an additional measure of quality assurance
against defective devices.
IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-supply current. Iddq stands for quiescent Idd, or quiescent power-supply current. Majority of IC’sare manufactured using complementary metal–oxide–semiconductor (CMOS) technology. In steady state, when all switching transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a defect-free CMOS circuit is negligible (on the order of few nanoamperes). However, in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (Vdd) to ground (Gnd) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of magnitude higher than the fault-free leakage current.Thus, by monitoring the power-supply current, one may distinguish between faulty and fault-free circuits.
IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-supply current. Iddq stands for quiescent Idd, or quiescent power-supply current. Majority of IC’sare manufactured using complementary metal–oxide–semiconductor (CMOS) technology. In steady state, when all switching transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a defect-free CMOS circuit is negligible (on the order of few nanoamperes). However, in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (Vdd) to ground (Gnd) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of magnitude higher than the fault-free leakage current.Thus, by monitoring the power-supply current, one may distinguish between faulty and fault-free circuits.
Ques:- Why do IDDQ Testing?
Ans:- For functional testing, a tester applies a sequence of input
data and detects the results in the sequence of output data. Then, the output
sequence is compared against the expected behavior of the device. An advantage
of functional testing is that it exercises the device as it would actually be
used in the target application. However, this type of testing has only a
limited ability to tests the integrity of a device's internal nodes.
with
functional testing only, an internal defect could slide by undetected.
The methodology for scan testing is all the sequential elements of the device are connected into chains and used as primary inputs and primary outputs for testing purposes. Using automatic test-pattern generation (ATPG) techniques, you have the capability to test a much larger number of internal faults than with functional testing alone. The goal of ATPG is to set all nodes of the circuit to both 0 and 1, and to propagate any defects to nodes where they can be detected by test equipment.
Using both functional and scan testing you greatly increases your odds at finding an internal defect, but what if the defect is not controllable or can't be observed? That is where IDDQ testing can help.
The methodology for scan testing is all the sequential elements of the device are connected into chains and used as primary inputs and primary outputs for testing purposes. Using automatic test-pattern generation (ATPG) techniques, you have the capability to test a much larger number of internal faults than with functional testing alone. The goal of ATPG is to set all nodes of the circuit to both 0 and 1, and to propagate any defects to nodes where they can be detected by test equipment.
Using both functional and scan testing you greatly increases your odds at finding an internal defect, but what if the defect is not controllable or can't be observed? That is where IDDQ testing can help.
Ques:- why do we need to put first negative edge flops followed
by positive edge flops in the scan chain?
Ans:- The rule is there should not
be 2 shift during one clock period. So if you put +ve edge flop followed by -ve
edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is
small) in one clock period. But if you put -ve edge flop then +ve edge flop,
then there is no chance of that. because the +ve edge come in the next period.
Or if ur
This
will depend on the nature of clock involved in your scan design.
If
Clock is RTZ then chain should be : negedge ->posedge
If clock is non RTZ then it should be vice-versa
reason is value loaded on first flop should not pass on to next FF in same cycle.
If clock is non RTZ then it should be vice-versa
reason is value loaded on first flop should not pass on to next FF in same cycle.
Ques:- How to toggle reset to get coverage
?
Ans:-
If the reset is asynchronous (and properly bypassed during scan), you can
declare the reset pin as a clock during ATPG, and ATPG will toggle it
accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults on the reset. If you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to declare the reset as a clock when running transition fault ATPG. You can also try to run the patterns that toggles the reset as a clock pin at a reduced speed on the tester, if you worry about transition fault coverage on reset.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults on the reset. If you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to declare the reset as a clock when running transition fault ATPG. You can also try to run the patterns that toggles the reset as a clock pin at a reduced speed on the tester, if you worry about transition fault coverage on reset.
