1. What is sequential Depth In DFT? How does it improve coverage?
Ans: FastScan performs clock sequential test generation if you specify a non-zero sequential depth.
Clock sequential identification selects scannable cells by cutting sequential loops and limiting sequential depth based on the -Depth switch. Typically, this method is used to create structured partial scan designs that can use the FastScan clock sequential ATPG algorithm.
Setting the -Sequential switch to either 0 (the default) or 1 results in patterns with a
maximum sequential depth of one, but FastScan creates clock sequential patterns only if the setting is 1 or higher.
The maximum allowable sequential depth is 255 (a typical depth would range from
2 to 5).
Coverage Improvement :
Testable faults become ATPG_untestable faults because of constraints, or limitations,
placed on the ATPG tool (such as a pin constraint or an insufficient sequential depth).
These faults may be possible-detectable, or detectable, if you remove some constraint, or change some limitation, on the test generator (such as removing a pin constraint or changing the sequential depth).
Also,(while using named capture procedure) gradually add more capture procedures with higher sequential depth until the test coverage goal is achieved or the pattern count limit is reached.
2. What is the difference between flops and scan flops?
Ans: Difference between scan flop and simple flops becomes more easy to understand when we know why do we need scan flop!!
Need of scan flop:
The goal of scan design is to make a difficult-to-test sequential circuit behave (during the testing process) like an easier-to-test combinational circuit. Achieving this goal involves replacing sequential elements with scannable sequential elements (scan cells/scan flops) and then stitching the scan cells together into scan registers, or scan chains. You can then use these serially connected scan cells to shift data in and out when the design is in scan mode.
“Before Scan” design is difficult to initialize to a known state, making it difficult to both control the internal circuitry and observe its behavior using the primary inputs and outputs of the design. In a "Scan design" scan memory elements (scan flops) replace the original memory elements (normal flops) imparting controllability and observability to the design (prime requirement for the design being testable), when shifting is enabled.
3. What is robust / non_robust test for path delay faults?
Ans: Non -Robust tests:
A pair of at-speed vectors that test a path delay fault; fault detection is not guaranteed, because it depends on other delays in the circuit.
Robust Tests:
A pair of at-speed vectors that test a path delay fault independent of other delays or delay faults in the circuit.
4. What are the techniques used to reduce pattern count without losing coverage ?
Ans: The number of test patterns that you need to achieve full coverage depends on the design size. Different ATPG tools offer different compression and pattern ordering techniques to help reduce pattern count.
fault models beyond stuck-at typically require pattern counts that are much larger than those for stuck-at only.
For Pattern reduction, first step is the chain balancing during Stitching or scan insertion. If your chains are balanced, Tool needs to insert less dummy patterns for reaching till required flop.
Also we can include compression on the chains where we have constraints on the pins of device.This means if we are having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your chain length (flops per scan chain).
5. Are the faults on the resets of the flops are detected? if so how are they detected?
Ans: Yes the faults on reset of the flop are detectable. It is detected in the following way
1) Define the reset pin as clock in the tdl
2) Let us assume that the reset of the flop is active low. Keep the reset as 'high' and scan in '1' in to the flop (during this scan enable is 'high')
3)As we have scan-in '1' the Q of the flop will have '1'
4) Make the scan-enable 'low' and toggle the reset(i.e. make it low). This is allowed because we have declared the reset as clock.
5) As reset is 'low' the flop need to get reset and whatever the value in the flop will become '0'
6) Then strobe for '0', while shifting-out the contents from the flop.
7) If the output while shifting out is '0', it means the reset pin of the flop is not stuck-at 1. Otherwise it is stuck at '1'.
Note:
1. In test mode all the flops should have a asynchronous reset.
2. The reset pins of all flops should be controllable from Top (Chip) level.
If your design contains a lot of synchronous reset flops. Then since during AC (transdly) testing these reset line faults are not targeted for AC, Constraining the reset to off state is the best way.
Ans: FastScan performs clock sequential test generation if you specify a non-zero sequential depth.
Clock sequential identification selects scannable cells by cutting sequential loops and limiting sequential depth based on the -Depth switch. Typically, this method is used to create structured partial scan designs that can use the FastScan clock sequential ATPG algorithm.
Setting the -Sequential switch to either 0 (the default) or 1 results in patterns with a
maximum sequential depth of one, but FastScan creates clock sequential patterns only if the setting is 1 or higher.
The maximum allowable sequential depth is 255 (a typical depth would range from
2 to 5).
Coverage Improvement :
Testable faults become ATPG_untestable faults because of constraints, or limitations,
placed on the ATPG tool (such as a pin constraint or an insufficient sequential depth).
These faults may be possible-detectable, or detectable, if you remove some constraint, or change some limitation, on the test generator (such as removing a pin constraint or changing the sequential depth).
Also,(while using named capture procedure) gradually add more capture procedures with higher sequential depth until the test coverage goal is achieved or the pattern count limit is reached.
2. What is the difference between flops and scan flops?
Ans: Difference between scan flop and simple flops becomes more easy to understand when we know why do we need scan flop!!
Need of scan flop:
The goal of scan design is to make a difficult-to-test sequential circuit behave (during the testing process) like an easier-to-test combinational circuit. Achieving this goal involves replacing sequential elements with scannable sequential elements (scan cells/scan flops) and then stitching the scan cells together into scan registers, or scan chains. You can then use these serially connected scan cells to shift data in and out when the design is in scan mode.
“Before Scan” design is difficult to initialize to a known state, making it difficult to both control the internal circuitry and observe its behavior using the primary inputs and outputs of the design. In a "Scan design" scan memory elements (scan flops) replace the original memory elements (normal flops) imparting controllability and observability to the design (prime requirement for the design being testable), when shifting is enabled.
3. What is robust / non_robust test for path delay faults?
Ans: Non -Robust tests:
A pair of at-speed vectors that test a path delay fault; fault detection is not guaranteed, because it depends on other delays in the circuit.
Robust Tests:
A pair of at-speed vectors that test a path delay fault independent of other delays or delay faults in the circuit.
4. What are the techniques used to reduce pattern count without losing coverage ?
Ans: The number of test patterns that you need to achieve full coverage depends on the design size. Different ATPG tools offer different compression and pattern ordering techniques to help reduce pattern count.
fault models beyond stuck-at typically require pattern counts that are much larger than those for stuck-at only.
For Pattern reduction, first step is the chain balancing during Stitching or scan insertion. If your chains are balanced, Tool needs to insert less dummy patterns for reaching till required flop.
Also we can include compression on the chains where we have constraints on the pins of device.This means if we are having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your chain length (flops per scan chain).
5. Are the faults on the resets of the flops are detected? if so how are they detected?
Ans: Yes the faults on reset of the flop are detectable. It is detected in the following way
1) Define the reset pin as clock in the tdl
2) Let us assume that the reset of the flop is active low. Keep the reset as 'high' and scan in '1' in to the flop (during this scan enable is 'high')
3)As we have scan-in '1' the Q of the flop will have '1'
4) Make the scan-enable 'low' and toggle the reset(i.e. make it low). This is allowed because we have declared the reset as clock.
5) As reset is 'low' the flop need to get reset and whatever the value in the flop will become '0'
6) Then strobe for '0', while shifting-out the contents from the flop.
7) If the output while shifting out is '0', it means the reset pin of the flop is not stuck-at 1. Otherwise it is stuck at '1'.
Note:
1. In test mode all the flops should have a asynchronous reset.
2. The reset pins of all flops should be controllable from Top (Chip) level.
If your design contains a lot of synchronous reset flops. Then since during AC (transdly) testing these reset line faults are not targeted for AC, Constraining the reset to off state is the best way.
