41. By full scan methodology do we mean that every single flop in the design is a part of the scan chain? And if we have multiple scan chains instead of one, as it is in present designs, can it still be called full scan methodology?
In a perfect world, full scan means every flip-flop, but in the real world, many flops can be unscanned, and the design is still considered full scan. In some cases, the ATPG tool can test through unscanned flops without a major impact to fault coverage. Designs using one or many scan chains are equally valid as full scan designs.
Apart from the conventional mux FF scan architecture, there are many others like the Level Sensitive scan and the clocked scan etc. How are these better or worse than the muxed FF technique?
LSSD is really a sub-specialty in the industry as a whole only a few companies use it, but it is effective. For scan purposes, it does not suffer from the hold time issues that mux-scan normally does, but area-wise, it's not as good.
Clock-scan uses a separate scan-clock for each flop - I've never seen it used in industry, but that's just me. The problem with it is that you must route two clock trees around the chip instead of one - a virtual show-stopper in these days of congested routing.
42. What are the thinks to be considered in scan stitching?
Scan stitching is done can be done in one of three ways:
1) Use the synthesis tool (DFT compiler or equivalent)
2) A DFT scan tool (such as DFT Architect)
3) The place and route tool
Some of the things to think about are:
1) How many scan ports do you have available? This will determine, in part, the number of scan chains. The scan chains need to be balanced in length to be as efficient as possible, for test-time/data volume.
2) Clocks - will you use flops from different clock domains in the same chain? If so, the clock domains need to be *reasonably* skew balanced for the chains to work properly. Also, lockup-latches will be necessary where the scan path crosses the clock domains for safe operation (if stitching.
3) Are there negative edge flops in the design? If so the tool will always place the negedge flops, as a group, ahead of the posedge flops.
43. why first negative edge flops followed by positive edge flops in the scan chain?
Well that's so the chain will shift data in and out properly. The idea is that each bit of the data shifting into the chain should traverse the chain one flop at a time.
Given a clock that is defined with an off-state of 0, a positive edge comes before a negative edge in time, right?
Now imagine in a scan chain, a posedge FF followed by a negedge FF. During any given clock period, the data that is latched into the posedge FF will also be latched into the negedge FF as well - in the same period. This is called a feed-through, and is generally not an optimal situation for the ATPG.
However, if the insertion tool puts the negedge flops all grouped at the front of the chain, then the boundary between the negede flops and posedge flops will be a negedge FF followed by a posedge FF. Since the positive edge of the clock comes before the negative edge, the data will be properly held up at the negedge FF until the next clock period.
I am doing scan stitching for a block which contains say two instances of prestitched blocks.
I need to connect top-level scan ports to scan ports of these blocks instances.
For example:
top block contains 5 chains in that 3 chains stitched for top-level logic.
Now for remaining scan ports I need to be connect the scan ports of stitched sub module instances
Say module is M1 and instantiated two times (M1 is stitched block)
B/C/D/M1_inst1
X/Y/Z/M1_inst2
I need to connect the top level block scan ports to scan port of the submodule inst B/C/D/M1_inst1.
As shown below
Scan_in[3] to B/C/D/M1_inst1.scan_in[0]
Scan_en to B/C/D/M1_inst1.scan_in[0]
Scan_out[3] to B/C/D/M1_inst1.scan_out[0]
Similarly for other instance.
The requirement is to maintain the hierarchy.
47. I am using RTL (RC) complier for scan stitching.
Is there any command in RC or DC for connect the ports?
I tried the below DC command but this is not supported for the available version W-2004.12-SP5
*****************************************
connect_pin [get_pins U1/Z] [find pin mid1/bot1/U3/A]
In DC, you will need a DFT compiler license to stitch is properly, as it does more than just connect the scan chains. It checks for any DRC errors, so your chains are intact. The DFT compiler documentation asks you to create a CTL model of the sub-blocks, so I am not sure if it is applicable to your implementation.
Without DFT compiler, you can try to hook it up manually, then try to extract the chain using an ATPG tool to see if the chains are intact.
48. I have in my design 3 types of flops.
1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?
Yes, it is possible.
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge CLK domain flip-flops before posedge CLK domain flip-flops, i.e., negedge CLK FFs are closer to scan input, and posedge CLK FFs are closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a significantly larger clock tree than RCO_CLK clock tree, then it is better to put RCO_CLK domain FFs at the end of the chain. Otherwise, you may need to skew your clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut
49. I would like to know about scan pin sharing with bidirectional pins.
I added control logic for these pins using or & and gates to make them work as inputs and outputs respectively. But during scan chain tracing its giving error as it is not able to trace from bidirectional pins shared as scanouts.
Constraining these pins to Z ,the dftadvisor traced the scan chains.
Why is this so even after adding control logic?
The correct way to deal with this is to constrain the bidi to Z, if u want to use it as SO or to mask the o/p of the bidi , if it has to be used as SI ( as adviced by FS).
By add control logic, u'r basically modifying the design, which may not be the correct way to go about it, as it may affect the functionality.
In any case, after u added the control logic, did u constrain the control logic i/ps during atpg?
50. How to fix S29 violations (Dependent slave may not hold the same value as master) The design basically has a LOCKUP latch as master feeding a scan-flop. Could you please explain why this violation occurs and how to go about fixing it. It should not be an issue. But can you be secific which tool is giving violation?
I have used DFT Advisor to insert a scan chain, but it seems the tool screwed up my netlist. It has connected the clock inputs of some of the flip flops to the output of some combo blocks. I have heard some people say DFTA is not a good tool for the purpose of scan insertion. Can you tell me what must have gone wrong.
Another thing that I have observed is: when i take the scan inserted netlist and perform timing analysis on it using DC, I find that the tool disables some CLK to Q timing arcs of some flops in order to avoid combo loops.
At least, i never saw this kind of behavior in DFTA. i have been using DFTA for last 5years. Did you run equivalence checking between your prescan netlist vs post scan netlist. Usually DFTA is not doing anything other replacing the flops to scan. Sometimes if you already have combinational feedback loop, it tries to break that path. you can control this, by adding a test logic.
In a perfect world, full scan means every flip-flop, but in the real world, many flops can be unscanned, and the design is still considered full scan. In some cases, the ATPG tool can test through unscanned flops without a major impact to fault coverage. Designs using one or many scan chains are equally valid as full scan designs.
Apart from the conventional mux FF scan architecture, there are many others like the Level Sensitive scan and the clocked scan etc. How are these better or worse than the muxed FF technique?
LSSD is really a sub-specialty in the industry as a whole only a few companies use it, but it is effective. For scan purposes, it does not suffer from the hold time issues that mux-scan normally does, but area-wise, it's not as good.
Clock-scan uses a separate scan-clock for each flop - I've never seen it used in industry, but that's just me. The problem with it is that you must route two clock trees around the chip instead of one - a virtual show-stopper in these days of congested routing.
42. What are the thinks to be considered in scan stitching?
Scan stitching is done can be done in one of three ways:
1) Use the synthesis tool (DFT compiler or equivalent)
2) A DFT scan tool (such as DFT Architect)
3) The place and route tool
Some of the things to think about are:
1) How many scan ports do you have available? This will determine, in part, the number of scan chains. The scan chains need to be balanced in length to be as efficient as possible, for test-time/data volume.
2) Clocks - will you use flops from different clock domains in the same chain? If so, the clock domains need to be *reasonably* skew balanced for the chains to work properly. Also, lockup-latches will be necessary where the scan path crosses the clock domains for safe operation (if stitching.
3) Are there negative edge flops in the design? If so the tool will always place the negedge flops, as a group, ahead of the posedge flops.
43. why first negative edge flops followed by positive edge flops in the scan chain?
Well that's so the chain will shift data in and out properly. The idea is that each bit of the data shifting into the chain should traverse the chain one flop at a time.
Given a clock that is defined with an off-state of 0, a positive edge comes before a negative edge in time, right?
Now imagine in a scan chain, a posedge FF followed by a negedge FF. During any given clock period, the data that is latched into the posedge FF will also be latched into the negedge FF as well - in the same period. This is called a feed-through, and is generally not an optimal situation for the ATPG.
However, if the insertion tool puts the negedge flops all grouped at the front of the chain, then the boundary between the negede flops and posedge flops will be a negedge FF followed by a posedge FF. Since the positive edge of the clock comes before the negative edge, the data will be properly held up at the negedge FF until the next clock period.
I am doing scan stitching for a block which contains say two instances of prestitched blocks.
I need to connect top-level scan ports to scan ports of these blocks instances.
For example:
top block contains 5 chains in that 3 chains stitched for top-level logic.
Now for remaining scan ports I need to be connect the scan ports of stitched sub module instances
Say module is M1 and instantiated two times (M1 is stitched block)
B/C/D/M1_inst1
X/Y/Z/M1_inst2
I need to connect the top level block scan ports to scan port of the submodule inst B/C/D/M1_inst1.
As shown below
Scan_in[3] to B/C/D/M1_inst1.scan_in[0]
Scan_en to B/C/D/M1_inst1.scan_in[0]
Scan_out[3] to B/C/D/M1_inst1.scan_out[0]
Similarly for other instance.
The requirement is to maintain the hierarchy.
47. I am using RTL (RC) complier for scan stitching.
Is there any command in RC or DC for connect the ports?
I tried the below DC command but this is not supported for the available version W-2004.12-SP5
*****************************************
connect_pin [get_pins U1/Z] [find pin mid1/bot1/U3/A]
In DC, you will need a DFT compiler license to stitch is properly, as it does more than just connect the scan chains. It checks for any DRC errors, so your chains are intact. The DFT compiler documentation asks you to create a CTL model of the sub-blocks, so I am not sure if it is applicable to your implementation.
Without DFT compiler, you can try to hook it up manually, then try to extract the chain using an ATPG tool to see if the chains are intact.
48. I have in my design 3 types of flops.
1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?
Yes, it is possible.
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge CLK domain flip-flops before posedge CLK domain flip-flops, i.e., negedge CLK FFs are closer to scan input, and posedge CLK FFs are closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a significantly larger clock tree than RCO_CLK clock tree, then it is better to put RCO_CLK domain FFs at the end of the chain. Otherwise, you may need to skew your clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut
49. I would like to know about scan pin sharing with bidirectional pins.
I added control logic for these pins using or & and gates to make them work as inputs and outputs respectively. But during scan chain tracing its giving error as it is not able to trace from bidirectional pins shared as scanouts.
Constraining these pins to Z ,the dftadvisor traced the scan chains.
Why is this so even after adding control logic?
The correct way to deal with this is to constrain the bidi to Z, if u want to use it as SO or to mask the o/p of the bidi , if it has to be used as SI ( as adviced by FS).
By add control logic, u'r basically modifying the design, which may not be the correct way to go about it, as it may affect the functionality.
In any case, after u added the control logic, did u constrain the control logic i/ps during atpg?
50. How to fix S29 violations (Dependent slave may not hold the same value as master) The design basically has a LOCKUP latch as master feeding a scan-flop. Could you please explain why this violation occurs and how to go about fixing it. It should not be an issue. But can you be secific which tool is giving violation?
I have used DFT Advisor to insert a scan chain, but it seems the tool screwed up my netlist. It has connected the clock inputs of some of the flip flops to the output of some combo blocks. I have heard some people say DFTA is not a good tool for the purpose of scan insertion. Can you tell me what must have gone wrong.
Another thing that I have observed is: when i take the scan inserted netlist and perform timing analysis on it using DC, I find that the tool disables some CLK to Q timing arcs of some flops in order to avoid combo loops.
At least, i never saw this kind of behavior in DFTA. i have been using DFTA for last 5years. Did you run equivalence checking between your prescan netlist vs post scan netlist. Usually DFTA is not doing anything other replacing the flops to scan. Sometimes if you already have combinational feedback loop, it tries to break that path. you can control this, by adding a test logic.
