What is meant by
virtual clock definition and why do i need it?
Ans: Virtual clock is mainly used to model the I/O timing
specification. Based on what clock the output/input pads are passing the data.
What are the
various timing-paths which i should take care in my STA runs? Ans:
1. Timing path starting from an input-port and ending at the output port(purely combinational path).
2. Timing path starting from an input-port and ending at the register.
3. Timing path starting from an Register and ending at the output-port.
4. Timing path starting from an register and ending at the register.
1. Timing path starting from an input-port and ending at the output port(purely combinational path).
2. Timing path starting from an input-port and ending at the register.
3. Timing path starting from an Register and ending at the output-port.
4. Timing path starting from an register and ending at the register.
How to solve
setup & Hold violations in the design?
Ans: To solve setup violation
1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)
To solve Hold Violations
1. Adding delay/buffer[as buffer offers lesser delay, we go for special Delay cells whose functionality Y=A, but with more delay]
2. Making the launch flop clock reaching delayed
3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip]
Ans: To solve setup violation
1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)
To solve Hold Violations
1. Adding delay/buffer[as buffer offers lesser delay, we go for special Delay cells whose functionality Y=A, but with more delay]
2. Making the launch flop clock reaching delayed
3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip]
What is the implication of
a combinatorial feedback loops in design testability?
The
presence of feedback loops should be avoided at any stage of the design, by
periodically checking for it, using the lint or synthesis tools. The presence
of the feedback loop causes races and hazards in the design, and 104 RTL Design
leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be tested with any ATPG algorithm. Hence, combinatorial loops should be avoided in the logic.
leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be tested with any ATPG algorithm. Hence, combinatorial loops should be avoided in the logic.
When
are DFT and Formal verification used?
Ans: DFT:
· manufacturing defects like stuck at "0" or "1".
· Test for set of rules followed during the initial design stage.
Formal verification:
· Verification of the operation of the design, i.e, to see if the design follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.
Ans: DFT:
· manufacturing defects like stuck at "0" or "1".
· Test for set of rules followed during the initial design stage.
Formal verification:
· Verification of the operation of the design, i.e, to see if the design follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.
Ques
: What is the significance of contamination delay in sequential circuit timing?
Ans: Look at the figure below. tcd is the contamination delay.
Contamination delay tells you if you meet the hold time of a flip flop. To understand this better please look at the sequential circuit below.
The contamination delay of the data path in a sequential circuit is critical for the hold time at the flip flop where it is exiting, in this case R2.
Mathematically, th(R2) <= tcd(R1) + tcd(CL2)
Contamination delay is also called tmin and Propagation delay is also called tmax in many data sheets.
Ans: Look at the figure below. tcd is the contamination delay.
Contamination delay tells you if you meet the hold time of a flip flop. To understand this better please look at the sequential circuit below.
The contamination delay of the data path in a sequential circuit is critical for the hold time at the flip flop where it is exiting, in this case R2.
Mathematically, th(R2) <= tcd(R1) + tcd(CL2)
Contamination delay is also called tmin and Propagation delay is also called tmax in many data sheets.
