DFT Q&A - Part 15

What is your design style for scanning?

If your design is predominantly edge-triggered, use the multiplexed flip-flop, clocked scan, or clocked LSSD scan style.

If your design has a mix of latches and flip-flops, use the clocked scan or LSSD scan style.

If your design is predominately level-sensitive, use the LSSD scan style.

Is it possible to reconvert the scan flip flop to normal flip flop?

You can convert the unused flops back to normal flops in DC , and the tool does that automatically. The command for the same is "set_dft_insertion_configuration-unscan true".

All the flops which are not on the scan chains will be converted back to normal flop.

can anyone tell me for a design how can we decide how many scan chains we require?...
another question is in a particular scan chain how many flops should be put? is it dependent on the technology or is it dependent on designer or on the customer requirement?

scan chian number depend on the clock domain and max flipflops. Don't mix different clock domains and clock edges to aviod timing issue.
and longer chian will increase test time, < 1000k ff's per chain.

There are a number of factors to decide the number of scan chains and length of each scan chain.

1. Look for your ATE specification to find how many scan chains are supported. If length of scan chain is very long, then the tester time increases and hence your cost

2. If you are using scan compression, then your scan compression methodology will determine the maximum length of each scan chain

Whether Positive skew is good for Setup? How?

positive skew is similar to useful skew , it is nothing but delaying capture clock by skew value correct than the normal launch clock value when ever you delay the capture clock surely you gain that my margin which can reduce in your setup violation. If you want to visualize properly, you can think like if you have more period then surely setup violation will reduce correct. it is similar concept.

Negative skew is bad for setup?

similar to my earlier answer here you are reducing the capture clock.

Positive skew is bad for hold? Negative skew is good for hold?

for example: FF1 --> FF2 --> FF3
case 1: All FF[flip flop ] has zero skew.
analysis: You have a setup violation path from FF1 to FF2.
Work around : Trying to optimize the datapath from FF1 to FF2 , you cannot do it , as the path is already optimized. Now what is the only option left is playing safely rather marginally with clock.
So you are planning for skewing the capture flip flop clock that is FF2, delaying , so assume you met with the setup violation across FF1 to FF2.

Another scenario comes, you had delayed your FF2 more, so you have a hold violation to FF3.
hope the concept is clear.

In STA report, if we find any hold violation, it can be remedied by adding buffers? Whether it will cause setup violation? Then how much to add and on what basis?

Assuming you have hold violation, you cannot go on apply on adding buffers on the data path. Before doing this you need to check the setup margin across the endpoint and see.
There could be scenario's where in path passing through a cell A you have setup and path passing through cell B input you have a hold violation, you have to apply specify back-trace and apply to that specific inputs only and not on the endpoint register straight away.

Uncertanity you are adding is for your margin's / jitter / process variations and things like that, reducing uncertanity is not a correct option to reduce your violation count. It is like taking from your saving's account and spending!!!

What are the various ways to reduce Clock Insertion Delay in the Design

1. Number of Clock sinks
2. Balancing two different clock frequencies
3. Placement of clock sinks.
4. Placement of Clock gating cells
5. Clock tree buffers/inverters drive strength's
6. Clock Transition
7. Placement of Clock gating cells and the clock sinks
8. Combinational cells in the path of clocks (say clock dividers, muxes, clockgates) .

What are the measures taken in the Design achieving better Yield?

Better yield could be achieved by reducing the possibility of manufacturability flaws. Guarantying the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.

• Create more powerful stringent run set files with pessimistic spacing/short rules.
• Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it.
• For via-reliability issues, use redundant vias, to reduce the chances for via-breakage.
• In order to design for yield-enhancement, design systems, this could have optimal redundancy, like repairable memories.
• Optimal placing of de-coupling capacitances reduces the power-surges.
• Doubling the width of the non-critical nets, clock-nets can increase the yield parameter.
• Ensure that the poly-orientation is maintained.

What are the measures or precautions to be taken in the Design when the chip has both analog and digital portions?

Designing for Optimal integration of Analog and Digital

• As today's IC has analog components also inbuilt, some design practices are required for optimal integration.
• Ensure in the floor planning stage that the analog block and the digital block are not sitting close-by, to reduce the noise.
• Ensure that there exists separate ground for digital and analog ground to reduce the noise.
• Place appropriate guard-rings around the analog-macro.
• Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion.
• Perform techniques like clock-dithering for the digital portion.

What is local-skew, global-skew, and useful-skew mean?

Local skew: The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Global skew: The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

What is the difference between latches and flip-flops based designs?

Latches are level-sensitive and flip-flops are edge sensitive. Latch based design and flop based design is that latch allows time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex.

How many minimum modes should qualify STA for a chip?
1. Scan Shift mode
2. Scan Capture mode
3. MBIST mode
4. Functional modes for Each Interface
5. Boundary scan mode
6. scan-compression mode
How many minimum process lots, should STA be qualified?
1. Fast corner
2. Slow corner
3. Typical corner
How many minimum Timing, Should STA be qualified?
1. Normal delay mode (with out applying duration)
2. On-chip variation mode (duration applied)

3. SI mode (Signal integrity cross talk impact on STA)


What are the various Timing Paths in a Chip?
1. Path starting from Input Data pad and Ending at Register pin.
2. Path starting from clock-pin of a Register and Ending at Data pin of a Register (Reg-to-Reg path).
3. Path starting from output of a Register and Ends at output pad of a chip.
4. Path starting from input data pad and ends at output data pad (pure combo path).