66. Why do we go for toggle fault
modeling? I think suck-at model also detects the faults which are detected by
toggle fault model. How tester applies patterns during toggle fault detection?
Toggle
faults are used mostly for code coverage metrics (for verification). You are
right that stuck-at is a super-set of that. I myself have never put 'toggle'
patterns on a tester.
Toggle
coverage is also used to measure the effectiveness of burn-in patterns.
In
the old days, where CMOS technology is not as leaky, some folks used toggle
patterns for IDDQ testing. However, pseudo stuck-at faults were proven to be
far superior than toggle patterns for IDDQ.
67. Effect of C4 violation on ATPG?
If
you don't declare rst as a clock, and constrain it to its inactive state, can
you get Tetramax to pass drc?
The
C4 violation is telling you that it can't make a difference in the state of any
flop when it tries to toggle rst - so maybe it's not a reset after all. Or
maybe it's gated off in scan mode?
In
this case, like Siyad said, maybe remove it from consideration as a clock, and
things will clear up. And then you might want to look into the design and see
if you intended to render it ineffective - it will result in a loss of
coverage...
When
I did observe the fanout of the reset, it indeed is getting gated in the
design.
Now,
I am trying to bypass this gated logic of rst manually by inserting a mux with
one input of mux as rst and other input as gate output and the test mode signal
as the select line of mux and then connect the mux output to the flop rst pin.
Is it okay to do this. Can this solve the C4 violation at the post dft drc
stage of the design.
Now
when I utilize this scan inserted netlist with the above modification (mux) and
the .spf to generate coverage with Tetramax. Will the effect of C4 violation be
subsided.
68. What is the difference between
FastScan and Flex Test?
On what basis do we select between
these two tools?
FlexTest
is a limited capacity 'sequential' ATPG tool - originally targeted for use with
small, non-scan or limited scan blocks. It can also give you fault coverage of
a given pattern set for the same. It's not used widely anymore, that I know of.
There's really no decision to make 'between' these two tools, because they are
for a different purpose. FastScan is for scanned circuits.
69. Why we loose coverage when we
constrain pins?
In
general, whenever you constrain any pins of your device, you take away the
ability of the ATPG to toggle that pin and check it (and its effects) in both
states. Sometimes when you constrain a pin, it will have negligble effect.
Sometimes it will have far ranging effects on fault coverage.
70. My design contain more clock
gating logic, how it affect DC and AC (At speed) coverage?
A
general mode of Clock Gating Cell contains two pins enable(EN) and test
enable(TE) pins. (Enable of latch = EN or TE)
We
will be working on TE pins in testmode.
If
TE is connected to Scan Enable then entire Clock gating cell will be covered
during ATPG. (All faults will be covered)
So
I dont think there is any coverage loss during ATPG
Please
see follwing link for more details
http://www.vlsichipdesign.com/clockondemand.html 
