61. What is difference between launch on
shift and launch on capture?
Advantage and disadvantage of each?
AC
scan test is a 2 pattern test, the first pattern launches a transition at the
soure flip-flop(s), and the second captures the transition at the destination
flip-flop(s). Hence, we need two clock pulses for each AC test.
There
are two ways to achieve this. The first way is to add another clock pulse
during scan capture (while your scan enable is inactive). This is called Launch
on Capture (LOC).
Code:
Launch
on Capture
2 fast pulses
L C
___
___ _
_ ___
___
clock
__| |__| |________| |_| |_________| |___|
|____
_______________ _____________________
scanen |__________|
The
other way is to rely on the last shift clock (while scan enable is still
active) to launch the transition (1st pattern), and use 1 clock pulse in the
capture cycle as the 2nd pattern to capture the transition. This is called
Launch on Shift (LOS).
Code:
Launch
on Shift
L C
___
___ _ ___
___
clock
__| |__| |___| |_____________| |___|
|____
_____________ _____________________
scanen |_________|
In
general, to make sure the transition reaches the capture flip-flop in time, the
delay between the launch and capture cycles should be your cycle time (or the
actual path delay, for those who run transition tests faster than at-speed).
As
you can see, to run LOS at-speed, your scan enable must switch at-speed also.
This is usually problematic in layout, since you need to either treat the scan
enable signal as a clock net (require clock tree synthesis with accurate
delay/skews), or pipeline the scan enable signal, which increases the
area/complexity of your scan enable.
I
have seen publications that claim either LOS gives you higher transition fault
coverage than LOC, or vice versa. I believe this is design dependent, and it
depends on the complexity of the logic cone(s) driving the source flip-flop(s).
If the logic cone(s) are simple, it gives ATPG a greater degree of freedom to
generate the appropriate 2nd pattern in LOC. Notice that the 2nd pattern in LOS
is always 1 bit shifted from the 1st pattern. On the other hand, if the cone is
complex, it may be hard to generate the appropriate 2nd pattern through the
logic, making LOS coverage numbers more attractive.
62. What all needs to be taken care in
scan stitching to get the good coverage?
If
you are using Mentor DFTAdvisor or Synopsys DFT Compiler, cleaning up
pre-stitch drc errors and most of the warnings (especially clock warnings) will
generally lead to good fault coverage.
If
coverage is still low after cleaning drc errors/warnings, then there may be
issues inherent to the design that causes low coverage (redundant logic,
complex reconvergent fanouts, black boxes, constrained nets, etc.)
Both
Mentor
62. How to toggle reset to get
coverage ?
If
the reset is asynchronous (and properly bypassed during scan), you can declare
the reset pin as a clock during ATPG, and ATPG will toggle it accordingly to
get faults on reset pin.
If
the reset is synchronous, you can treat the reset pin as a normal data pin, and
ATPG should be able to cover faults on the reset.
Be
careful, however, if you run transition fault ATPG. Reset usually cannot toggle
at-speed, so you may not want to declare the reset as a clock when running
transition fault ATPG.
You
can also try to run the patterns that toggle the reset as a clock pin at a
reduced speed on the tester, if you worry about transition fault coverage on
reset.
63. What are Pattern Faults? I have
seen the definition in cadence ET manual but didn't understand.
A
pattern fault is a fault model created by IBM Testbench folks (later acquired
by Cadence and became Test Encounter). Instead of using a standard fault model
like stuck-at, transition, etc., you can use truth tables to describe what the
fault free and faulty behavior is for each gate type.
The
advantage is that you can use pattern faults to guide ATPG to generate patterns
that would not be generated with other fault models. For example, in a 2 input
AND gate, to cover single stuck-at faults, you need only 3 patterns, 01, 10,
and 11. If you want to force ATPG to generate a pattern for the 00 case in
every AND gate, you can define a pattern fault with 00 as its sensitization.
A
pattern fault is a mechanism used by Encounter Test to model static or dynamic
defects that are not easily, or may be impossible to be represented by stuck-at
pin faults. A pattern fault is basically a statement of 1) the requirements to
excite the defect being modeled; and 2) the effect the defect being modeled has
on the circuit once it has been excited. For the current release of Encounter
Test, fault excitation requirements are specified as logic values required to
be on circuit pins or nets of a (sub-) circuit. For dynamic pattern faults, the
required values include a (two) pattern sequence or required values to excite
the defect.
Encounter Test automatically generates pattern
faults to represent defects not possible to represent as pin stuck-at pin
faults on LATCH, TSD and XOR primitives. The customer or technology library
provider can add additional pattern faults for any sub-circuit used in the
circuit design being processed. These user defined pattern faults will be
repeated in the Encounter Test fault model for each instance of the
sub-circuit.
64. What is the difference between
test pattern and test vector?
The
terms are sometimes used interchangeably. Me, I tend to say that a test pattern
is a set of test vectors.
However,
the ATPG tools generally give you stats that claim a certain number of
'patterns', but personally, I would call them 'vectors'.
65. What is a BUS Primitive and
clock_PO pattern?
A
bus primitive is just a DFT model of a bus - a net that has more than one
driver. It's important that you constrain it during test.
