DFT Q&A - Part 22

Ques : Can we have same BIST controller for different memories?
If yes what are the requirements?

Ans : Sharing one BIST controller with several memory instances is very common in the industry. Chips with hundreds of memory instances are very common these days, so BIST sharing is almost a given with these kinds of devices.
The most important factors with BIST sharing are:
1. Sharing similar types of memories, e.g. embedded DRAM require different BIST algorithms from SRAM, thus sharing may not be very economical.
2. Physical location of the memories on the chip. If you have a large chip, you may want to consider using several BIST controllers to cover different sections of the chip.

There are many levels of sharing BIST. You can share the basic FSM or test sequencer but not the rest of BIST, or you can share the full address/control/write data generation portion but not the response comparison. You can also share the response comparison, but once you do that, the memories that share the same reposnse comparator must be tested serially.

Ques : What is a seed for Logic BIST?
What is re-seeding?
How re-seeding is done in SocBIST and DBIST?

Ans : A 'seed' for an LFSR is the starting value of the register that provides stimulus. Remember an LFSR generates a pseudo-random value (which repeats itself, given enough clocks) - but if the register is large enough, there's not enough time to go through the whole repeating sequence. So if you go part way through, and then 'reseed' the LFSR, you can get fault coverage improvement in a more efficient manner.

Ques : What is the relationship between Cost and Yield of a chip?
Is there any derivation for the same?

Ans : The relationship between cost and yield is pretty complex stuff, and depends on the technology node, the manufacturer, and many other factors.
The best one can say is that they are normally inversely proportional - the better your yield, the lower the cost, because the fixed cost of putting wafers through the fab will result in more devices going to the customer.
However, I can write a test that gives me 100% yield (no test at all), but I'll get a large percentage of my devices returned, and lose a ton of respect (and market share).

Ques :  Is Logic BIST going to take over the conventional scan methodology in industrial applications in near future?

Ans : Very unlikely. There are too many advantages that scan has over Logic BIST that it cannot be usually replaced.
For example, Logic BIST lack the full controllability and observability that scan provides, which may be essential for debug, or coverage improvement.

Ques : What problems could be expected on silicon in scan mode? I am talking about the problems that could hinder running chip in scan mode?
like I have heard that sometimes testing in scan mode doesn't work at the intended frequency it is designed for?

Ans : You can avoid having problems in the silicon by simulating your scan vectors with back-annotated timing information (SDF). However, even then you may have some problems, because normally, simulation is not run with all the same timing corners that are used to close timing.
When someone says that they are not able to run scan at-speed, it usually means that the ATPG was run without considering all the false- and multi-cycle-paths that are present in the design. These paths don't generally run at-speed. This happens a lot in multi-clock domain circuits.
Also very common is that the scan chains don't shift properly - they may have hold-time violations. This is hard to overcome, but a partial set of patterns may be possible if you can figure out where the problem is. Again, if you simulate the scan shift pre-silicon, you may avoid this.

wht is the diffrence between verification and dft?
difference between defect, fault and failure?
how can we perform scan operation?
wht is serial and parallel loading?
wht is the difference between sequential and combinational atpg?
wht is atpg?
wht is drc violation?
wht is fault model?
how many fault models are there?
wht is scan stiching?
different command option....
wht is bist?
wht is bisa?

formulas for test data volume, scan chains in data compression mode..
What you mean by scan chain reordering?

How logic transition fault is different from memory transition fault.
What are RAM sequential patterns?
Diff b/w Named Capture Procedures and Clock Procedures
How much is your design count? Complexity?
What is possible cause of simulation mismatches when you simulate the generated ATPG patterns? What is right way to debug them?
How do you solve coverage issues?

what is normal mode and at-speed mode?
what is mbist?
what is dft coverage? how to get high dft coverage?
normal flow for dft ?

What is the difference between structural and functional vectors?
Ans: http://www.eetasia.com/ARTICLES/2004DEC/B/2004DEC01_ICT_ST_TA.pdf

What the major problem faced in dft with tri-state buffers and how is it resolved.
Ans: 1. The major problem is from the tester end, not all testers are able to measure Z.
2. For the IDDQ vectors, there can be no Z in the design, there is quite a lot of current when a pin is in Z state. A floating bus that is a bus with z on it will drain too much of current and hence loosing the objective of the iddq vectors.
3. Next these tri-state buffers are generally used for sharing the bus, so there has to be a dft logic so there is no contention on these bus during test.

Give three conditions where bus contention can occur.
Ans: 1. During the shift ( i.e load of the scan chains )
2, During the forcing of the PIs
3. After the capture clock, the flops may capture any thing which may lead to the contentions.

Which is advantageous, launch at shift or capture launch.
Ans:

http://www.stridge.com/Stridge_articles/ac_scan_testing.htm
http://scholar.lib.vt.edu/theses/available/etd-02062003-145930/unrestricted/etd.pdf
Also a new technique is being used now is to pipe line the scan enable, and negating the scan enable in advance so that by the time of capture is to be done, the scan enable is low.

what is P1500 funda?
Ans: It is similar to BSDA but at the chip level , instead of the board level. The major difference is that in the BSDA
we are sure that the chips are OK and then do the board testing. But in the case of P1500 , we are not sure of anything, each and every core has to be tested.

How to achieve high fault coverage. How to increase it.
Ans: 1. 100% scan design
2. More number of test points
3. No X’s in the design
4. Use sequential patterns
5. Completely defined netlist, i.e there should be no floating outputs, or un connected inputs.
6. There should be logic to certain that there would be no contentions on the bus
7. Avoid floating bus using bus keepers.

Latch - how is it used in dft for sync two clock domains.
Ans: Latches are used as lockup latches in the scan chains. These are inserted in the chains where ever there is a change in the clock domain. By clock domain we mean, two clocks or the same clock with phase difference.
Let us have a condition here to explain the things; we have a design with 2 clocks CLK1 and CLK2. There is a single chain in the design, which means that the scan chain have flops which can be clocked by either of the clock.
The tool by default will order the flops in the scan chain such that first we have one clock domain's flop followed by the other domain flops. Let us consider that the CLK2 flops follows CLK1 flops.
Now consider the flop which is at the boundary that is the one where the output of the CLK1's flop is going to the CLK2's scan_in. Clock skew between these successive scan-storage cells must be less than the propagation delay between the scan output of the first storage cell and the scan input of the next storage cell. Otherwise, data slippage may occur. Thus, data that latches into the last flop of CLK1 also latches into the first flop of CLK2. This situation results in an error because the CLK2's flop should latch the CLK1's "old" data rather than its "new" data.
To overcome this issue we add the lock up latch where ever there are clock domain crossing. In our example we would add a lock-up latch which has an active high enable and is being controlled by inverted of CLK1. Thus becomes transparent only when CLKA goes low and effectively adds a half clock of hold time to the output of the last flip-flop of clock domain CLK1.

Explain Fault types ?
Ans: The different fault types are
1. Stuck at fault model : The node is modeled to be stuck at some value 0 or 1 depending on what we are targeting.
2. Iddq fault model : This is similar to the stuck at fault model but here instead of measuring the voltage we measure the current . In a CMOS design at the quiescent state, ideally there is suppose to no current in the silicon, if there is current then some node has either shorted to ground or to the power.
3. Transition fault model : This is considered to stuck at fault model within a time window. The value of the node changes but not within the time ,at which it should change .For detecting such faults we have two vector for each pattern one for launching the fault and the other to capture the fault. The time between the launch and the capture is supposed to be equal to the time at which the chip would normally function. This is the reason it is all called at-speed test.
4. Path delay fault model : In this fault model ,instead of concentrating on a single gate of the netlist ,we generally are concern with a collection of gates which forms a valid path in the design. These are generally the critical paths of the design. Here again we have two vectors for each pattern. Do let me know if you know what is a valid path ( don't feel offended I am just writing this because you are out of touch with all these technical jargons since long , otherwise I hope you must be knowing them).
The transition faults are also measured at the paths ends, but the major difference between the transition and the path delay is that in the path delay we give the path where as in the case of transition the tool itself selects the path for give fault.
The fault location for IDDQ, stuck-at and transition are same.
5. Bridging fault model : this is a new model which is gaining importance . In this case any two close lying net may effect the value of each other. There is generally a victim and another is a aggressor, so an aggressor forces some value on the victim . We first find the coupling capacitance of each net pair, then depending on the specs we may select some nets which have coupling capacitance more then specified value, these are selected and then these become the fault locations for the ATPG.

Does the dft vectors test the functionality of the design also?
Ans: No the dft vectors does not test the functionality of the design. It can be otherwise that is we can use the functional vector to test fault grade them and use the same for finding the fault coverage using these vectors. The dft vectors are generated keeping the design in test mode , so they won't be beneficial for the functional mode. But note this that there may always be an overlap in the patterns.