DFT Q&A - Part 29

Ques:- Why latches (other than lock-up and clock gating) in design are bad for ATPG? We always loose coverage by putting them on transparent mode by constraining enable signal. How can we increase this coverage?

Ans:- I think you answered your own question regarding why we lose coverage,
"putting them on transparent mode by constraining enable signal".

Any logic driving the enable signal will lose some coverage due to this constraint.

If the enable signal is driven by a large cone of logic, you can increase the coverage by adding a "force transparent on" gate close to the enable of the latch, and add an observe flip-flop just before the added gate, so that most of the faults in the logic cone can be recovered.
Without modifying the circuitry, recovering fault coverage in ATPG really depends on how these latches are used in the functional path.

Ques:- when both the Transition-delay and path_delay target for transition faults, why we should have two different methods to detect the same?

Ans:- Transition delay is similar to stuck-at atpg, except that it attempts to detect slow-to-rise and slow-to-fall nodes, rather than stuck-at-0 and stuck-at-1 nodes. A slow-to-rise fault at a node means that a transition from 0 to 1 on the node doesnot produce the correct results at the maximum operating speed of the design. Similarly a slow-to-fall fault means that a transition form 1 to 0 on a node doesnot produce the correct results at the maximum speed of the design.Transition delay fault targets single point defects.

The Path delay fault model is useful for testing and characterizing critical timing paths in the deisgn. Path delay fault tests exercise critical paths at-speed to detect whether the path is too slow because of manufacturing detects or variations.
Path delay fault testing targets physical defects that might affect distributed region of a chip. For example, incorrect field oxide thicknesses could lead to slower signal propogation times, which could cause transitions along a critical path to arrive too late.

Note:------------------

If we attain 100% coverage with transition atpg test then we dont need to do the path delay test.
But this is not the case in most of our designs. Then how can we GUARANTEE that all the critical paths are targeted by Transition ATPG
so we give the critical path to the atpg tool and tell it to generate patterns for it
this is called path delay

Ques:- What is Burn in test? Why is it done?

Ans:- Burn-in is the process by which device infant mortality failures are
accelerated through application of temperature and stress voltages for
specific periods of time. The goal of burn-in is to stress the device as much
as possible thereby accelerating device infant mortality rate. Since scan
based test has higher coverage, scan test vectors are used to stress the logic
portion of the device. This can either be done by performing device level
ATPG by applying external test patterns on onchip LBIST. Memory BIST is
used for memories
Note :-----------------

High toggled atpg vectors are generated to sensitize the internal nodes of the chip so that chip will get more stress

Ques:-- If for a DFT production set we have both PATH Delay and Transition patterns which scheme should be done first ?

Ans:- Its always better to do Path_delay first and then the transition delay.

Path_delay- start flop and end flop are given by the user.(i.e) transition through a well defined path-(More effective)

Transition-Start and end flop is decided by the tool,so trasition may happen through a shorter or longer path-(Less effective)

1)path delay basically targets for all the critical paths in the design.
2)Generate the path_delay patterns for all the critical paths in the design and write down the faults for the same.
3) Generate the transition delay pattern by loading the faults on the path_delay, such that the faults detected in the path_delay are not Re-targeted.
4) The major reason to follow the above sequence is in trans-delay we are not sure weather a transition has really happened through the critical path.

(A)-If we do the transition-ATPG first, we are not sure whether the transition has happened through the critical path,In such case we may not have pattern which may catch the fault through the critical path,but the fault may be detected through some other shorter paths which may add the faults to the detected list.
(B)If we run a path_delay after the above step(A) then we may have a pattern for the critical path,but it leads to the pattern redundancy because we have already a transition pattern for the same fault.

Ques:-- What is IDDQ Testing?

Ans:- IDDQ Testing can detect certain types of circuit faults in CMOS circuits that are difficult or impossible to detect by other methods.  IDDQ testing, when used with standard functional or scan testing, provides an additional measure of quality assurance against defective devices.

IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-supply current. Iddq stands for quiescent Idd, or quiescent power-supply current. Majority of IC’sare manufactured using complementary metal–oxide–semiconductor (CMOS) technology. In steady state, when all switching transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a defect-free CMOS circuit is negligible (on the order of few nanoamperes). However, in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (Vdd) to ground (Gnd) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of magnitude higher than the fault-free leakage current.Thus, by monitoring the power-supply current, one may distinguish between faulty and fault-free circuits.

Ques:- Why do IDDQ Testing?

Ans:- For functional testing, a tester applies a sequence of input data and detects the results in the sequence of output data. Then, the output sequence is compared against the expected behavior of the device. An advantage of functional testing is that it exercises the device as it would actually be used in the target application. However, this type of testing has only a limited ability to tests the integrity of a device's internal nodes.

with functional testing only, an internal defect could slide by undetected.
The methodology for scan testing is all the sequential elements of the device are connected into chains and used as primary inputs and primary outputs for testing purposes. Using automatic test-pattern generation (ATPG) techniques, you have the capability to test a much larger number of internal faults than with functional testing alone. The goal of ATPG is to set all nodes of the circuit to both 0 and 1, and to propagate any defects to nodes where they can be detected by test equipment.
Using both functional and scan testing you greatly increases your odds at finding an internal defect, but what if the defect is not controllable or can't be observed? That is where IDDQ testing can help.

Ques:- why do we need to put first negative edge flops followed by positive edge flops in the scan chain?

Ans:- The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge then you need to insert a lock up latch (if skew is small).

This will depend on the nature of clock involved in your scan design. 

If Clock is RTZ then chain should be : negedge ->posedge
If clock is non RTZ then it should be vice-versa

reason is value loaded on first flop should not pass on to next FF in same cycle.

Ques:- How to toggle reset to get coverage ?

Ans:- If the reset is asynchronous (and properly bypassed during scan), you can declare the reset pin as a clock during ATPG, and ATPG will toggle it accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults on the reset. If you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to declare the reset as a clock when running transition fault ATPG. You can also try to run the patterns that toggles the reset as a clock pin at a reduced speed on the tester, if you worry about transition fault coverage on reset.

DFT Q&A - Part 28

Ques:- Suggest the design techniques for improving the testability?

Ans:

Prevention is better than Cure...

The above saying tells everything related to this information.

The scan design or design-for-testability (DFT) has been a standard in ASIC design  flow for most designers, Obtaining high fault coverage for a design depends on the quality of the implemented DFT logic, and most \real-world" designs suffer from a variety of DFT related issues, which if left unsolved, result in reduced fault coverage. Designs with gated clocks and resets may not be good for testing, but the design style is used frequently. Since the clock pins of scan cells with gated clocks are not controlled by the primary input clock ports, a scan test is impossible without repair. The situation is the same for gated resets. Repair has been performed by inserting an additional primary input port `test-mode' and test logic in order to feed the top level clock (or reset) signal to the scan cells. This modication results in untestable faults due to the DFT constraints on the `test-mode' port, which lowers fault coverage.

There are some common reasons due to which we generally observe DRC violations. Here I am discussing those common areas and possible fixes if they are un-avoidable reasons.

In order to ensure a successful scan-based design (i.e., achieve high fault coverage), one must design with testability in mind throughout the design process. If the designer is aware of design structures that can derail testing efforts, he or she can adopt alternative design techniques whenever possible.

1. Avoid Bus Contention

One of the bigest hurdle in system on chip (SOC) with respect to ATPG is controlling the internal tristate bus structures.

Bus contention occurs when two drivers are driving different values on the same bus. Since bus contention causes severe damage to the chip, it is important to prevent bus conflicts during normal operation as well as during scan. So, one should handle internal tristates  with care and avoid bus contention by design.

In most designs, a bus has more than one driver. To avoid bus contention in normal operation, designers must make sure only one tristate gate at a time is selected. To satisfy testability rules, designers must set the signals for the bus drivers so that contention is eliminated in the test phase.

I can't say do not design internal tristate bus structures bus structures. But, I can suggest, if possible, never implement designs with internal tristate bus structures. If you can’t follow this rule, then implement the fewest possible internal tristate-bus structures and guarantee by design that no bus contention can occur on any internal bus during scan

testing.

Be careful of two important while handling contention issues.

1.Ensure that there is no contention on the tristate buses during scan-shift operations.

2. ensure that there is no possible contention on the internal tristate buses during the capture cycles during scan testing.

Most of the DFT tools are intelligent enough to take care of internal tri state buses during test logic insertion and will made proper fixes. And, some fixes has to be made manually. Even most of the ATPG tools will warn about the bus-contentions. Ultimately, test engineer has to take decision whether to generate the vectors that cause contention or to avoid it.

It is suggestable to avoid it or fully-decode the busses else, it may effect the chip productivity. 

2. Avoid Gated Clocks

Gated clocks are generally used as one of the power saving techniques. These clocks fan-in through at least one combinational gate apart of buffers and inverters. Enable signal of the gated clocks makes the followed sequential elemets in ON/OFF states. Unfortunately, if the clocks of these flip-flops cannot be controlled from primary inputs, these gated clocks make it impossible to scan in data. Removing these flip-flops from the scan chain is one solution, but this results in a loss of fault coverage.

One can employ one of the following solutions as per the design and/or requirements.

Solution-1 is just excluding DFF from the scan chain. This solution costs test coverage loss.

In Solution-2 the “Scan Mode” input controls a multiplexer that changes/bypass the clock source for DFF. In this case, output of AND gate is un-observable and all faults into the AND gate are ATPG un-testable. To overcome this situation, one can add test-point at the output of AND gate as shown below. By adding this logic to the solution-2 provide better ATPG test coverage.

3. Bypass Pulse generators and internally generated clocks

Here comes the internally generated clocks/pulse generators (PLLs, frequency dividers, pulse generators). Before going into the topic, I strongly suggest that DFT Engineer should always question him/her self that whether he/she can control a particular internal logic element via. primary inputs or not.  It not add test logic to control that element through primary inputs. Here the thumb rule is that the primary inputs (scan clocks, reset etc.) should be controllable from any primary input. Derived clocks can render a large part of the design untestable because the flip-flops are not controllable from any primary input.

So, do not use clock dividers in ATPG test mode. If your design contains clock dividers, bypass them in ATPG test mode. Use the Scan Mode signal to control the source of the internal clocks, so that in ATPG test mode you can bypass the clock divider and source the internal clocks from the primary CLK output.

On the bottom line, do not use phase-locked loops (PLLs) as clock sources and bypass the clocks while in ATPG test mode.For pulse generators in the design, one can disable the pulse generators by adding disabling logic or can bypass the pulse generator output with access from a top-level input port as mentioned below.

4. Asynchronous Set/Reset Signals

It is strongly recommended to avoid asynchronous resets in the design. If it is unavoidable one can go ahead with it bearing some test coverage loss. There are different ways to handle asynchronous resets during test logic insertion to get a better test coverage.

There are different situations generally one would face with reset signals.

1.Reset used as data:

In general, reset signal goes to the reset pin of the sequential elements. We discuss in the next point what if the reset is asynchronous reset. In some designs, reset is used as data. i.e. Reset pin goes to the data input of the sequential elements. In such situations, there are two different ways to handle this.

Option-1:

Place a MUX logic at the Reset net, which is synchronously driven to the sequential cell. One input of the MUX would be an actual reset signal; the other input is constant 1|0, which is the inactive state of the Reset. The select line is the ScanMode signal.  But the problem with this case is the Reset logic is still not observed, which reduces the coverage. This method provides direct control over the asynchronous reset for scan testing. This method will make the reset controllable and will detect faults on the asynchronous reset of all registers. The disadvantage of the method is that it blocks the functional reset and therefore faults in the reset logic circuitry might be untestable because of the ScanMode constraint. Also, an extra port has to be identify for the external reset pin.

Option-2:

This is very tricky job. It is just to play with the reset signal making it either active high or active low based on the type of flops (active high or active low reset).

Assume, flops have active high reset.

During Shift Mode:

Control the reset signal fed to the flop such that it is   active low and keep the scan flop in the active state. And the operation follows the regular scan operation where the data is first shifted into the scan flip-flops holding at active low.

During Hold & Capture Mode:

In this case the vectors are generated without applying any clocks during the capture operation, and the logic feeding into the SET/RESET inputs (the Asynchronous path) of the scan flip-flops is tested. The operation follows the regular scan operation where the data is first shifted into the scan flip-flops holding at active state. Then during hold and capture, de-activate those scan flops by proper controlling of the reset signal fed into it. so that the signals are allowed to propagate through the reset logic and modify the values in the scan flip-flops. Finally the results are shifted out for comparison on the tester. This second option will improve the test coverage either.

Below figure shows you how to control the asynchronous reset signal fed into the flops.

Place an OR gate with one input as Scan Enable signal and the other input of OR gate is the async. reset signal fanout from the reset logic. One can use a dedicated signal in place of the Scan Enable signal.

This method provides control to disable asynchronous resets during scan shift only. The method makes the reset controllable and will detect faults on the asynchronous reset of all registers as well as test the reset logic circuitry.  The only disadvantage of this method is that the asynchronous resets will always be controlled by the internal logic and can't be disabled during scan capture. This could cause unwanted resets while attempting to test for other faults. As explained above, one can avoid these unwanted resets by using a dedicated external signal to control the disabling of the asynchronous resets during shift instead of using the main ScanEnable signal.

Note: To follow the 2nd option, one should be familiar with the corresponding tool command flow on which ATPG vectors are generating. All most all the ATPG tools will have a proper command flow to handle the asynchronous resets.

5. Avoid Cross coupled Gates

In some designs, one can observe SR latches. Though they are in expensive way of implementing latches, they create testability problems when both the inputs of cross coupled NAND gates are ant logic 1.

Add logic to make each cross-coupled NAND/NOR gate behave like a buffer

during testing as shown below. When the ScanMode signal is set to ‘1’ during test, the circuit converts the cross-coupled gates into two inverters

If possible, it is better to implement the latches using D-latches instead of cross-coupled SR latches. On the bottom line, as latches reduce the test coverage, avoid inferring latches in the design if possible.

6. Fix Bi-Directional ports

One should fix the bi-directional ports of the design. Ensure that the direction of Bi-directional ports are fixed to either input or output by controlling the enable signal of the bi-directional port.  If the enable signal is generated internally, proper DFT logic has to be employed. Or else, if the controlling signal is a primary port, provide proper logic value on the bi-di controlling port during the test to make the bi-di ports unidirectional.

If the primary DFT pads (scan enable, scan-ins, scan-outs, scan-clks etc.) are bi-directional, fix them and make the respective pads, uni-directional accordingly with the ScanMode signal.  For the pads, other than DFT ports, fix them using ScanEnable signal. This will improve the test coverage. 

Note:  If Scan Mode it self is bi-directional, be sure that the bi-di control pin is accessable to the ATE. So that, one can make the ScanMode signal to input by providing the proper value to the control pin during test.

If it is scan clock, scanenable, scanmode, scan-in ports fix their direction to input. If scan-out ports are bi-directional, fix their direction to output.

Following figure shows the fix for scan-clock which is bi-directional with internally generated control logic.

7. Avoid contention due to non tri-state inputs (Wired Logic)

Wired-AND Wired-OR logics leads to contention issues and should be avoided during the test. Most of the DFT tools have the ability to perform contention ability checks on buses and wired logic.

When a net has more than one driving object, wired-AND or wired-OR logic is introduced. A circuit re-modeling will subsequently be performed where wired-ANDs are replaced by AND gates and wire-ORs are replaced by OR gates.

8. Remove Redundant Logic and Test Point Addition

Remove Redundant Logic

This sounds un-reasonable. But still, if the design is not properly optimized and left with some redundant logic, be sure to optimize the logic properly. Most of the DFT tools will take care of optimizing the design.

Test Point Addition:

After test patterns and test coverage is generated by the ATPG tool, be sure to verify the pin-point locations where controllability and/or observability are insufficient. Insert test points at these locations when I/O pad limit is allowed and again rerun the ATPG for better coverage

9. Provide proper time margin for DFT inserted design

To improve a circuit’s fault coverage, one may have to add a DFT circuitry in the silicon.

If the designer does not leave room for DFT insertion, the newly created design may violate timing constraints. Thus, during the early design stage, it is important to leave, say

15%-20% timing margin for future DFT insertion. It is strongly recommended to re-simulate the DFT inserted design before submitting it to ATPG and layout

10. Floating Nets

Avoid floating nets in the design. This may cause unwanted leakage currents that leads to power failures. So, it is strongly recommended to verify for floating nets in the design before and after the DFT insertion.

11. Avoid Latches

Latches cannot be scanned unless they are converted to scan latches. Such a conversion creates an extremely large area overhead. If the latches are part of an embedded memory, it is possible to model all the latches together as a memory. Using a memory model can reduce the difficulty of generating patterns for faults near the latches; however, special

tests are required for the latches.

When latches are not part of the memory, a more general solution is to make the latches transparent during test mode. This takes care of the problem of propagating fault effects through the latches, but the faults on the enable logic of latches become completely untestable, reducing fault coverage. The best solution is to avoid using latches in designs as much as possible.

12. Try avoiding combinational feedback loops

What is a combinational loop?

It is a simple form of D-Latch.

Designs that contain combinationalfeedback loops have inherent testability problems. Combinationfeedback loops may introduce internal logic states to a design that scan-storage elements cannot control.

ATPG tools have a few methods for breaking combinational feedback loops. Some of these methods are less harmful to fault coverage than others, but all of them result in some loss of coverage. Therefore, you should avoid combinational feedback loops whenever possible. Most ATPG tools inform users of all the combinational-feedback loops present in a design. If you cannot avoid these feedback loops, then you should break the feedback loop by inserting an additional flip-flop that is present in the feedback path only during scan-test mode. This modification results in the highest fault coverage. If you cannot insert a flip-flop, then insert a multiplexer in the feedback path that drives a constant value during scan-test mode. This approach results in lower coverage than the flip-flop option but higher coverage than if you allow the tool to break the loop by assuming an unknown value as a result of the

loop.

Combinational feedback loops introduce sequential behavior into otherwise combinational logic, making it difficult to use combinational ATPG tools. In addition, such loops may lead to races and hazards, resulting in unpredictable circuit behavior. These loops are generally delay-dependent and therefore can't be tested with any ATPG algorithm.

Typically, designers will omit combinational feedback loops from their designs. However, the loops can be created unknowingly when two portions of a design done by different designers are tied together.

If creating combinational feedback loops are unavoidable, designers should add test logic to the design. This fix allows combinational feedback loops to be broken during testing by using a scan flip-flop.  One should break this loop during scan mode for the ATPG tool to predict the operation of the circuit.

DFT Q&A - Part 27

Ques:----- Can any body tell me 

1) What causes HOLD VIOLATIONS in DESIGN. 

2) How it effects DESIGN. 

3) What changes need to be done to make DESIGN work.

Ans:----

Hi Friend, 

1) What causes HOLD VIOLATIONS in DESIGN. 
Simply, data should be hold for some time (hold time) after the edge of the clock. So, if the data changes with the hold time might cause violation. In general, hold time will be fixed during backend work (during PNR) while building clock tree. If u r a frontend designer, concentrate on fixing setup time violations rather than hold violations. 

2) How it effects DESIGN. 
If a chip is done with some setup violations it can work by reducing the frequency. 
If achip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of the day. Hold vilations needs to be fixed. 

3) What changes need to be done to make DESIGN work. 
PNR tools will route and place the cells in such a way that no timing violations will occur. If still u face hold violations, u can manully work on it to fix. Manually place the cells to avoid hold violations, or in the worst case, u can keep some buffers in the datapath to avoid hold violations (but be sure setup timing is not effected.)

you said "If achip is done with hold violations, JUST DUMP the chip. " 
>why can't reducing the frequency to settle the hold violation as setup violation ? 
>could you explain it clearer ? 

Equation for Setup Time 
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter 

Equation for Hold Time 
Tclktoq + Tlogic - Tskew > Thold 

Note that Hold Time equation is independent of clk frequency(i.e Time period Tclk) 

key things to note from above equations 
a) once the silicon comes back , if u have setup time problem , u can 
increase the clock period (Tclk) to fix it , whereas if u have hold 
time problem , its a more serious problem and u will need a new 
metal fix tapeout . ( But u can still test the current chip using Low supply voltage, 
or High temperature or SS corner part that decrease hold time violation

Hi Friends, 

Pls. make a note that HOLD violations are dangerous than SETUP. To keep it simple way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here. 

T = Frequency of operation (can be variable) 
Tcq = Flop clock to Flop output delay (fixed/constant) 
Tcomb = Delay od the combinational logic between the Flops (can be variable) 
Tsetup = Setup time of a Flop (fixed/constant) 
Thold = Hold time of a Flop (fixed/constant) 
Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable) 

For SETUP, 
T >= Tcq + Tcomb + Tsetup - Tskew 

If you have setup time means u r violating the above rule. i.e some how the equation becomes 
T < Tcq + Tcomb + Tsetup - Tskew 

Now let us consider two cases. 

Case1: During the Design development phase itself. 

Now, you have three variables (T, Tcomb, Tskew.) to avoid the setup violation. 
T : Reduce the frequency such that u saticify T >= Tcq + Tcomb + Tsetup - Tskew. But do u think it is the correct solution. Obviously, NO. This is because we have other options to avoid setup violations right. 
Tcomb : If you reduce the combinational delay (between the Flops of violated path) such a way that T < Tcq + Tcomb + Tsetup - Tskew will become T >= Tcq + Tcomb + Tsetup - Tskew. So, the SETUP violation is avoided. How do u reduce the combinational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine. 
Tskew: If u increase the skew, u can change T < Tcq + Tcomb + Tsetup - Tskew to T >= Tcq + Tcomb + Tsetup - Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing. 

Case2: After the CHIP is manufatured and is in your hand. 

In this case, one cannot access the Tcomb and Tskew. Only the variable that can handle is T. 
So, Just reduce the frequency (T) such that the violated equation, T < Tcq + Tcomb + Tsetup - Tskew becomes violation free equation T >= Tcq + Tcomb + Tsetup - Tskew. 

So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency. 

For HOLD, 
Thold + Tskew <= Tcq + Tcomb 

If you have setup time means u r violating the above rule. i.e some how the equation becomes 
Thold + Tskew > Tcq + Tcomb and ur aim is to make Thold + Tskew <= Tcq + Tcomb 

Now let us consider two cases. 

Case1: During the Design development phase itself. 

You have two variables in hand (Tcomb, Tskew) to avoid HOLD violations. 
Tcomb: Increase the Tcomb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew > Tcq + Tcomb to Thold + Tskew <= Tcq + Tcomb. But this might effect the SETUP time as you are increasing the delay of combinational path. So this may not be the perfect solution always. 

Tskew : Reduce the clock skew so that you will land on Thold + Tskew <= Tcq + Tcomb. To reduce the clock skew, the best solution is to take the help of your PNR engineer. 

Case2: After the CHIP is manufatured and is in your hand. 

Do you see any variables that will fix the hold violations after manufaturing?????!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioning chips to the customers. 

So becareful with the HOLD violations. 

Note: One can get those equations if u put those scenarios on a paper and develop the timing diagrams. 

Hope I've explained it properly. 

Regards, 
xxxxxx. 


Hi xxxxx, 

It is nice information. Could you please give us more information on 

" u will need a new metal fix tapeout . ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease hold time violation)" 

It may give us more information on this topic. 

Thanks in advance. 

Regards, 
xxxxxxx

what i meant was , when u have hold time violation , u dont need to throw away chip and wait for 3 months for fixed chip to come back. in the meanwhile , by playing with voltage and temperature , u can do other functional tests on the chip . since normally hold time simulation are done at " FF corner , high voltage, low temperature " which is the pessimistic case for hold time , by decreasing voltage , using high temperature, and a SS corner chip , we may be lucky enough to find a part that works , to do other functional tests to catch any other bugs before next tapeout.