How
do u break combinational loops. (*)How does introducing TIEX will eliminate
combinational loop. [ I told him by forcing known value we can break the loop]
Ans: By adding a tiex gate we can break the combinational loop. First what is a combinational loop. The value is not stabilized, there are oscillation. So if we place a X gate at some place in the loop, we are not propagating the deterministic value which was causing the oscillations.
Adverse Effect : Any X in the design would reduce the coverage.
The second solution would be to place a buffer with unit delay. In this case you would require sequential patterns. Please note that we are not placing any Tiex or buffer with unit delay in the netlist, it is just that we are tellingur
What is scannability checking?
Ans: I think this relates to the scan chain integrity. The first pattern that is pattern0 in most of the ATPG tool is called the chain test pattern. This pattern is used to check the integrity of the scan chains, to see if the scan chains are shifting and loading properly; if the scan chains itself have a fault there is no use checking the full chip using this chain.
Give three Clock drc rules and how to fix them.
Ans: 1. Clock not controllable from the top. ( Use mux to controll the same)
2. When all the clocks are in off state , the latches should be transparent ( add logic to make them transparent)
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data may be affected by new captured data. ( for FASTSCAN : clock_off simulation on and for TetraMAX : set atpg -resim_basic_scan_pattern
)
What does test procedure files have?
Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
What problems u faced while inserting test points.
Ans: The problems u faces while inserting test points ,
I don't think there is any problem, except
1. Selecting the best candidate location for the test points.
2. Area over head
Ans: By adding a tiex gate we can break the combinational loop. First what is a combinational loop. The value is not stabilized, there are oscillation. So if we place a X gate at some place in the loop, we are not propagating the deterministic value which was causing the oscillations.
Adverse Effect : Any X in the design would reduce the coverage.
The second solution would be to place a buffer with unit delay. In this case you would require sequential patterns. Please note that we are not placing any Tiex or buffer with unit delay in the netlist, it is just that we are telling
What is scannability checking?
Ans: I think this relates to the scan chain integrity. The first pattern that is pattern0 in most of the ATPG tool is called the chain test pattern. This pattern is used to check the integrity of the scan chains, to see if the scan chains are shifting and loading properly; if the scan chains itself have a fault there is no use checking the full chip using this chain.
Give three Clock drc rules and how to fix them.
Ans: 1. Clock not controllable from the top. ( Use mux to controll the same)
2. When all the clocks are in off state , the latches should be transparent ( add logic to make them transparent)
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data may be affected by new captured data. ( for FASTSCAN : clock_off simulation on and for TetraMAX : set atpg -resim_basic_scan_pattern
) What does test procedure files have?
Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
What problems u faced while inserting test points.
Ans: The problems u faces while inserting test points ,
I don't think there is any problem, except
1. Selecting the best candidate location for the test points.
2. Area over head
