Ans:
The
following figure shows a synchronous alternative to the gated clock using a
data path. The flip-flop is clocked at every clock cycle and the data path is
controlled by an enable. When the enable is Low, the multiplexer feeds the
output of the register back on itself. When the enable is High, new data is fed
to the flip-flop and the register changes its state
Ques : A very good interview question... What is difference between setup and hold time. The interviewer was looking for one specific reason , and its really a good answer too..The hint is hold time doesn't depend on clock, why is it so...?
Ans: Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup violation. But for hold time, you are only concerned with one edge and does not basically depend on clock frequency
Ques : A very good interview question... What is difference between setup and hold time. The interviewer was looking for one specific reason , and its really a good answer too..The hint is hold time doesn't depend on clock, why is it so...?
Ans: Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup violation. But for hold time, you are only concerned with one edge and does not basically depend on clock frequency
Ques
:What is Stuck-at fault ?
Ans: A Stuck-at fault is a particular fault model used by fault simulators and Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.
Ans: A Stuck-at fault is a particular fault model used by fault simulators and Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.
Ques : What is
Clock Gating ?
Ans: Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry, and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.
Ans: Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry, and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit.
Ques : How to fix the hold/setup violation in scan path (Q to SI path)?
Ans : If the violations are small,
as in most designs with well balanced clock trees, the place and route tools
can generally fix these by adding small buffers/inverters. Some smart scan
reordering tools will take a slightly farther scan flip-flop to avoid hold
problems.
If the violations are big, due to large clock skews, the best way to solve this is to add a data lockup latch.
I have always wondered why scan chain reordering tools don't take clock skew information into consideration. Not sure if the latest tools uses this vital information.
If the violations are big, due to large clock skews, the best way to solve this is to add a data lockup latch.
I have always wondered why scan chain reordering tools don't take clock skew information into consideration. Not sure if the latest tools uses this vital information.
I think the
tools look first to reduce congestion, by reducing the number of clock buffers
in the scan path, which will minimize hold time violations, but there are
always some left, so your process has to include a step where the post-route
netlist is re-analyzed for timing (both mission and scan mode), and any hold
violations left in the scan path are manually fixed.
Ques : I have 3 types of flops in
my design.
1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?
1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge CLK domain flip-flops before posedge CLK domain flip-flops, i.e., negedge CLK FFs are closer to scan input, and posedge CLK FFs are closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a significantly larger clock tree than RCO_CLK clock tree, then it is better to put RCO_CLK domain FFs at the end of the chain. Otherwise, you may need to skew your clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut
