Give three Clock drc rules and how to
fix them.
Ans: 1. Clock not controllable from the top. ( Use mux to controll the same)
2. When all the clocks are in off state , the latches should be transparent ( add logic to make them transparent)
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data may be affected by new captured data. ( for FASTSCAN : clock_off simulation on and for TetraMAX : set atpg -resim_basic_scan_pattern
)
What does test procedure files have?
Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
What problems u faced while inserting test points.
Ans: The problems u faces while inserting test points ,
I don't think there is any problem, except
1. Selecting the best candidate location for the test points.
2. Area over head
If enable pin of tri-state is 0, the output is Z. how does tool treat this Z as in DFT. How is Z handled.
Ans: It depends on the tester. We can customize the tool to generate the patterns
Ans: 1. Clock not controllable from the top. ( Use mux to controll the same)
2. When all the clocks are in off state , the latches should be transparent ( add logic to make them transparent)
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data may be affected by new captured data. ( for FASTSCAN : clock_off simulation on and for TetraMAX : set atpg -resim_basic_scan_pattern
) What does test procedure files have?
Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
What problems u faced while inserting test points.
Ans: The problems u faces while inserting test points ,
I don't think there is any problem, except
1. Selecting the best candidate location for the test points.
2. Area over head
If enable pin of tri-state is 0, the output is Z. how does tool treat this Z as in DFT. How is Z handled.
Ans: It depends on the tester. We can customize the tool to generate the patterns
How operating voltage can be used to
satisfy timing?
Ans: Higher operating voltage can cause faster slew, which sometimes can fix timing.
What is the difference between local-skew, global-skew and useful-skew?
Ans: Local-skew - skew between a reg2reg path
Global-skew - skew between all registers in a clock domain
useful-skew - to advance the clock in a reg2reg path in order to meet setup time.
What is meant by virtual clock definition and why do i need it?
Ans: Virtual clocks are defined on I/O because they real clock associated with them, however, they are considered start points and endpoints in STA, so they must have a clock. The latency is estimated to be the network latency of a clock tree, pre-cts.
Is it possible to reduce clock skew to zero
Ans: Not in a practical sense.
What are problems associated with skew and how to minimize it?
Ans: Skew is the difference in insertion delay to registers. If the skew is too large, then you fail timing.
How to solve setup and Hold violations in the design?
Ans: For hold only way to insert buffers (Correct)
For setup only way to upsize the cell and tweak the skew?
Or reduce the levels of logic from reg2reg, use fasted cells, swap pins, slow down the clock, etc...
Ans: Higher operating voltage can cause faster slew, which sometimes can fix timing.
What is the difference between local-skew, global-skew and useful-skew?
Ans: Local-skew - skew between a reg2reg path
Global-skew - skew between all registers in a clock domain
useful-skew - to advance the clock in a reg2reg path in order to meet setup time.
What is meant by virtual clock definition and why do i need it?
Ans: Virtual clocks are defined on I/O because they real clock associated with them, however, they are considered start points and endpoints in STA, so they must have a clock. The latency is estimated to be the network latency of a clock tree, pre-cts.
Is it possible to reduce clock skew to zero
Ans: Not in a practical sense.
What are problems associated with skew and how to minimize it?
Ans: Skew is the difference in insertion delay to registers. If the skew is too large, then you fail timing.
How to solve setup and Hold violations in the design?
Ans: For hold only way to insert buffers (Correct)
For setup only way to upsize the cell and tweak the skew?
Or reduce the levels of logic from reg2reg, use fasted cells, swap pins, slow down the clock, etc...
What are the violations which prevent
scan insertion?
Ans:
Scan design rules require that registers have the
functionality, in test mode, to be a cell within a large shift register. This
enables data to get into and out of the chip. The following violations prevent
a register from being scannable:
• The flip-flop clock signal
is uncontrollable.
• The latch is enabled at
the beginning of the clock cycle.
• The asynchronous controls
of registers are uncontrollable or are held active.
Uncontrollable
Clocks
This violation can be caused
by undefined or unconditioned clocks. DFT Compiler considers a clock to be
controlled only if both of these conditions are true:
• It is forced to a known
state at time = 0 in the clock period (which is the same as the “clock off
state” in TetraMAX).
•It changes state as a
result of the test clock toggling.
Latches Enabled at Beginning of Clock Cycle
Latches Enabled at Beginning of Clock Cycle
This violation applies only
when the scan style is set to level-sensitive scan design (LSSD). For a latch
to be scannable, the latch must be forced to hold its value at the beginning of
the cycle, when the clock is inactive. This violation can be caused by
undefined or unconditioned clocks.
This violation indicates
that there are registers that cannot be controlled by ATPG. If the violation is
not corrected, these registers will be unscannable and fault coverage will be reduced.
Asynchronous
Control Pins in Active
State
Asynchronous pins of a
register must be capable of being disabled by an input of the design.If they
cannot be disabled, this is reported as a violation. This violation can be
caused by asynchronous control signals (such as the preset or clear pin of the
flip-flop or latch) that are not properly conditioned before you run DFT
Compiler.
What are the violations which prevent data capture?
Ans: The violations are described in the following
sections:
• Clock Used As Data
• Black Box Feeds Into Clock
or Asynchronous Control
• Source Register Launch
Before Destination Register Capture
• Registered Clock-Gating
Circuitry
• Three-State Contention
• Clock Feeding Multiple
Register Inputs
What
are the violations which reduces fault coverage?
Ans:
Violations that can reduce fault coverage are
• Combinational Feedback
Loops
• Clocks That Interact With
Register Input
• Multiple Clocks That Feed
Into Latches and Flip-Flops
• Black Boxes
Combinational
Feedback Loops
An active (or sensitizable)
feedback loop reduces the fault coverage that ATPG can achieve by increasing
the difficulty of controlling values on paths containing parts of the loop.
Clocks That
Interact With Register Input
A clock that affects the
data input of a register reduces the fault coverage attainable by ATPG, because
ATPG pulses only one clock at a time, keeping all other clocks in their off states.
Attempting to fix this purely in the ATPG setup can result in timing hazards.
Black Boxes
Logic that drives or is
driven by black boxes cannot be tested because it is unobservable or uncontrollable.
This violation can drastically reduce fault coverage, because the logic that surrounds
the black box is unobservable or uncontrollable
Which scan styles are supported in your technology library?
Ans:
To make it possible to implement internal scan structures in the scan style you
select, appropriate scan cells must be present in the technology libraries
specified in the target_library
variable.
Use of sequential cells that
do not have a scan equivalent always results in a loss of fault coverage in
full-scan designs.
What is your design style?
Ans:
If your design is predominantly edge-triggered, use themultiplexed flip-flop,
clocked scan, or clocked LSSD scan style.
If your design has a mix of
latches and flip-flops, use the clocked scan or LSSD scan style.
If your design is
predominately level-sensitive, use the LSSD scan style.
How complete are the models in your technology
library?
Ans:
The quality and accuracy of the scan and nonscan sequential cell models in the
Synopsys technology library affect the behavior of DFT Compiler. Incorrect or
incomplete library models can cause incorrect results during test design rule
checking.
DFT Compiler requires a
complete functional model of a scan cell to perform test design rule checking.
The Library Compiler UNIGEN model supports complete functional modeling of all
supported scan cells. However, the usual sequential modeling syntax of Library
Compiler supports only complete functional modeling for multiplexed flip-flop
scan cells.
When the technology library
does not provide a functional model for a scan cell, the cell is a black box
for DFT Compiler.
What is Design For Test (DFT)?
Ans:
Designing
for the testability, in which the test merges, with the design in the earlier
process of the design, following what is called a design-for-test (DFT).
What is Testability?
Ans: Testability
is a design attribute that measures how easy it is to create a program to
comprehensively test a manufactured design's quality.
What is Functional Testing?
Ans: Functional
testing verifies that your circuit performs as it was intended to perform.
Testing of all possible input combinations grows exponentially as the number of
input increases. Thus in real time it may not be possible to test all the input
combinations.
What is Manufacturing Testing?
Ans: Manufacturing
testing verifies that your chip does not have manufacturing defects by focusing
on circuit structure rather than functional behavior. Manufacturing defects
include problems such as
Ø Power
or ground shorts
Ø Open
interconnect on the die due to dust particles
Ø Short
circuited source or drain on the transistor due to metal spike-through.
Manufacturing
defects might remain undetected by functional testing yet cause undesirable
behavior during circuit operation.
What Are Fault Models?
Ans: When
a manufacturing defect occurs, the physical defect has a logical effect on the
circuit behavior and chip may not work as intended. An open connection can
appear to float either high or low. A signal shorted to power appears to be
permanently high. A signal shorted to ground appears to be permanently low.
What is Stuck-at Fault Models?
Ans: The
stuck-at-0 fault means a signal that is permanently low regardless of the other
signals that normally control the node, as shown in Figure 1. The stuck-at-1 fault represents a signal that is
permanently high regardless of the other signals that normally control the
node. For example, assume that you have a
two-input AND gate that has stuck-at-0 fault on the output pin. As shown in
Figure 1-1, regardless of the logic level of the two inputs, the output is
always 0.
What is Controllability?
Ans: How
easy it is to control the inputs of any cell inside the design from the input
pads.
What is Observability?
Ans: How
easy it is to observe the outputs of any cell inside the design from the output
pads.
What is Scan design?
Ans: Scan
design is the most popular DFT technique and has high fault coverage results.
The idea is to control and observe the values in all the design's storage
elements so you can make the sequential circuit's test generation and fault
simulation tasks as simple as those of a combinational circuit.
What is Full Scan?
Ans: Full
scan is a scan design methodology that replaces all memory elements in the
design with their scan-able equivalents and then stitches them into scan chain.
Full scan can assure the high quality of the product. The idea is to control
and observe the values in all the design's storage elements so you can make the
sequential circuit's test generation and fault simulation tasks as simple as
those of a combinational circuit.
Full
Scan Benefits
The following are benefits
of employing a full scan strategy:
Ø Highly automated process. Using scan insertion
tools, the process for inserting full scan circuitry into a design is highly
automated, thus requiring very little manual effort.
Ø Highly effective, predictable method. Full scan
design is a highly effective, well-understood, and well-accepted method for
generating high-test coverage for your design.
Ø Assured quality. Full scan assures quality
because it tests most of the silicon.
What is Partial Scan?
Ans: The
full scan design makes all storage elements scannable; it will cost in terms of
silicon area and the timing. Because of these in some design we may not have
the luxury of having a full scan design. There comes the idea of Partial scan,
which is also a scan design methodology where only a fraction of the storage
elements in the design are replaced by their scannable equivalents and stitched
into scan chains. By carefully choosing which storage elements to be replaced
we can increase the testability of the design with minimal impact on the
design's area or timing. If the design cannot offer to accommodate the extra
delay added in critical path (due to added mux in the storage element), we can
exclude those critical flip-flops from the scan chain using partial scan.
Partial
Scan Benefits
Ø Reduced
impact on area.
Ø Reduced
impact on timing.
Ø More
flexibility between overhead and fault coverage.
What
are the different dft strategies?
Ans: At the highest level, there are two main approaches to DFT: ad hoc and structured. The following subsections discuss these DFT strategies.
Ans: At the highest level, there are two main approaches to DFT: ad hoc and structured. The following subsections discuss these DFT strategies.
Ad
Hoc DFT
Ad hoc DFT implies using
good design practices to enhance a design's testability, without making major
changes to the design style. Some ad hoc techniques include:
Ø Minimizing
redundant logic
Ø Minimizing
asynchronous logic
Ø Isolating
clocks from the logic
Ø Adding
internal control and observation points
Using these practices
throughout the design process improves the overall testability of the design.
Structured
DFT
Structured DFT provides a
more systematic and automatic approach to enhancing design testability.
Structured DFT's goal is to increase the controllability and observability of a
circuit. Various methods exist for accomplishing this. The most common methods
are
Ø The
scan design technique, which modifies the internal sequential circuitry of the
design.
Ø The
Built-in Self-Test (BIST) method, which inserts a device's testing function
within the device itself.
The
boundary scan, which increases board testability by adding circuitry to a chip.
