Ques : Say in my design some flops work at low frequency, in that
case,
How can we take care of flops of lower frequency when we do an at speed testing?
How can we take care of flops of lower frequency when we do an at speed testing?
Ans : It depends upon whether you
have independent scan clocks to control the different clock domains. If so you
can generate patterns that cover all the domains, and you just need to mask the
boundaries between domains.
But that's not the normal case. Many times people will use one scan clock to drive the whole circuit - and in this case, you will need to generate patterns for each clock domain separately, while masking or black boxing all the other domains.
But that's not the normal case. Many times people will use one scan clock to drive the whole circuit - and in this case, you will need to generate patterns for each clock domain separately, while masking or black boxing all the other domains.
Ques : What all needs to be taken care in scan stitching to get
the good coverage?
Ans : If you are using Mentor
DFTAdvisor or Synopsys DFT Compiler, cleaning up pre-stitch drc errors and most
of the warnings (especially clock warnings) will generally lead to good fault
coverage.
If coverage is still low after cleaning drc errors/warnings, then there may be issues inherent to the design that causes low coverage (redundant logic, complex reconvergent fanouts, black boxes, constrained nets, etc.)
BothMentor
If coverage is still low after cleaning drc errors/warnings, then there may be issues inherent to the design that causes low coverage (redundant logic, complex reconvergent fanouts, black boxes, constrained nets, etc.)
Both
Ques : How to toggle reset to get coverage ?
Ans : If the reset is asynchronous (and properly bypassed during
scan), you can declare the reset pin as a clock during ATPG, and ATPG will
toggle it accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults on the reset.
Be careful, however, if you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to declare the reset as a clock when running transition fault ATPG.
You can also try to run the patterns that toggle the reset as a clock pin at a reduced speed on the tester, if you worry about transition fault coverage on reset.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults on the reset.
Be careful, however, if you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to declare the reset as a clock when running transition fault ATPG.
You can also try to run the patterns that toggle the reset as a clock pin at a reduced speed on the tester, if you worry about transition fault coverage on reset.
Ques : What are Pattern
Faults?
Ans : A pattern fault is a fault model created by IBM Testbench folks
(later acquired by Cadence and became Test Encounter). Instead of using a
standard fault model like stuck-at, transition, etc., you can use truth tables
to describe what the fault free and faulty behavior is for each gate type.
The advantage is that you can use pattern faults to guide ATPG to generate patterns that would not be generated with other fault models. For example, in a 2 input AND gate, to cover single stuck-at faults, you need only 3 patterns, 01, 10, and 11. If you want to force ATPG to generate a pattern for the 00 case in every AND gate, you can define a pattern fault with 00 as its sensitization.
The advantage is that you can use pattern faults to guide ATPG to generate patterns that would not be generated with other fault models. For example, in a 2 input AND gate, to cover single stuck-at faults, you need only 3 patterns, 01, 10, and 11. If you want to force ATPG to generate a pattern for the 00 case in every AND gate, you can define a pattern fault with 00 as its sensitization.
A pattern
fault is a mechanism used by Encounter Test to model static or dynamic defects that
are not easily, or may be impossible to be represented by stuck-at pin faults.
A pattern fault is basically a statement of
1) the
requirements to excite the defect being modeled; and
2) the
effect the defect being modeled has on the circuit once it has been
excited. For the current release of Encounter Test, fault excitation requirements are
specified as logic values required to be on circuit pins or nets of a (sub-) circuit. For
dynamic pattern faults, the required values include a (two) pattern sequence or required values to excite the defect.
excited. For the current release of Encounter Test, fault excitation requirements are
specified as logic values required to be on circuit pins or nets of a (sub-) circuit. For
dynamic pattern faults, the required values include a (two) pattern sequence or required values to excite the defect.
Encounter Test automatically generates pattern faults to represent defects not possible to represent as pin stuck-at pin faults on LATCH, TSD and XOR primitives. The customer or technology library provider can add additional pattern faults for any sub-circuit used in the circuit design being processed. These user defined pattern faults will be repeated in the Encounter Test fault model for each instance of the sub-circuit.
Ques : What is the use of
compressor? Why can’t we use compressor for RAM?
Ans : You're getting your test
methodology mixed, I think, but you can test a ROM with a compressor - also
known as a MISR. That's done all the time. The idea is that the contents of the
ROM are simply read out, and fed into the MISR (multiple input shift register),
and the resulting signature is read out and compared with the expected
signature.
It's not so common to do that with RAMs, since both the write and read data are generated algorithmically.
However if your question is more general, the use of a compressor is usually to turn a large set of data into a smaller one, which is very handy for when access to the circuit, or bandwidth, is limited.
It's not so common to do that with RAMs, since both the write and read data are generated algorithmically.
However if your question is more general, the use of a compressor is usually to turn a large set of data into a smaller one, which is very handy for when access to the circuit, or bandwidth, is limited.
Ques : may I know what is the major difference between
transition and path delay fault models and which of them is an industrial
standard?
Ans : Transition delay and path
delay fault models both seek to describe defects which cause slow transitions
on gate inputs or outputs. The difference is that a path delay is more specific
- the whole path, from point a to point b is specified. It's a more stringent
case than a transition fault. To detect a transition fault, it is only required
that the ATPG generates a pattern to propagate that fault to a scanned flop.
The path selected may not be the worst case path.
Most people in the industry begin with transition faults, because the ATPG can generate patterns with decent coverage more easily. Then if desired, those patterns are augmented with a much smaller set of path delays that are determined to be critical (maybe those with the least margin as determined by the timing tool).
Most people in the industry begin with transition faults, because the ATPG can generate patterns with decent coverage more easily. Then if desired, those patterns are augmented with a much smaller set of path delays that are determined to be critical (maybe those with the least margin as determined by the timing tool).
Ques : What is memory redundancy & what is a repairable
memory?
Ans : Since memory is much more
dense than standard logic, it is more likely to fail in the presence of
manufacturing defects. In addition, many SoCs have a significant amount of
memory on-board, so the device's yield will be determined by the memory's
yield.
To combat this yield limitation, designers will implement memories with extra rows and/or columns. Then if a defect causes there to be just a small number of addresses to fail, an analysis algorithm is run to determine how one or more of the extra rows or columns can be substituted for the defective ones.
So the extra rows/columns are the redundancy, and the fact that they have been implemented makes it so that you can 'repair' a defective memory. It's not so much 'repair' as 'replace'
To combat this yield limitation, designers will implement memories with extra rows and/or columns. Then if a defect causes there to be just a small number of addresses to fail, an analysis algorithm is run to determine how one or more of the extra rows or columns can be substituted for the defective ones.
So the extra rows/columns are the redundancy, and the fact that they have been implemented makes it so that you can 'repair' a defective memory. It's not so much 'repair' as 'replace'
