25. What is PBIST?
Ans: PBIST is the TI Internal IP used to test the memories in the design popularly called as Programmable BIST. As design is moved to deep micron, knowing the nature of defect is very challenge in silicon. Hence we want to have programmable BIST to support algorithms that have been developed post silicon.
Key feature:-
=========
1. It can able to support test 8192 memories in the design.
2. Ability to run different algorithm even post silicon.
3. Support ROM based testing.
Programmable Built-In Self-Test (PBIST) is a memory DFT feature that incorporates all the required test systems into the chip itself.
PBIST was originally adopted by large memory chips that have high pin counts and operate at high frequencies, thereby exceeding the capability of production testers. The purpose of PBIST is to avoid developing and buying more sophisticated and very expensive testers.
PBIST or programmable built-in Self Test is a technique of memory testing. The PBIST strategy, as the above responders have mentioned are basically the same as MBIST.
The difference lies in the architecture and the hierarchy.
For the PBIST, there is only a single BIST controller for a group of memories, as against one controller per memory type in MBIST. In PBIST, memories are grouped under different groups, and are treated as separate memory instances. Each memory instance is accessed by a unique RGS, RDS and CSR value. The RDS value selects the return data slice.
The PBIST controller can be accessed through 3 interfaces: VLCT (Very low cost tester), ROM and CPU. This VLCT interface makes the PBIST programmable during testing of the device, as against MBIST, where the algorithms are hard-coded and cannot be changed once fixed.
Elaborating the terms used in the above respond that will add further clarity to the concept:
RGS, RDS, CSR... etc all these are PBIST internal configuration registers used for PBIST programming. All the configuration registers are memory mapped for access by the CPU through the VBUS interface in all modes.
Chip Select Register - CSR[31:0]
PBIST implements a chip select of up to 32 RAMs with a 32-bit register. When a READ or WRITE command is executed, the corresponding Chip Select is driven active and enables that RAM. At reset, the default value of the register is all 0s.
CSR is normally the same as the 32-bit decoded value of the 5-bit RDS. For a memory to be selected, the corresponding CSR bit pointed to by the RDS register should be set to 1. More than 1 CSR could be turned on at the same time to excite more than one memory simultaneously, but the return data will always be selected from one memory pointed to by the unique RDS.
We have a 32 bit RAM Configuration Register (RAMT[31:0]) which is internally divided into 6 registers, none of which have a default value after reset.
RGS, RDS are part of RAMT.
RAM Group Select [7:0] (same as RAMT[31:24])
In order to support more than 32 RAMs, this RAM grouping address register has been provided. This extends the total number of RAMs that can be tested from 32 to 8192 RAMs of 32 bits or less. RAMs with data width larger than 32 will be tested as more than one RAM and data logged separately.
Return Data select [7:0] (same as RAMT[23:16])
This register is for selecting memory return data for selected RGS group. 8 bits of RGS and 5 bits of RDS give flexibility to test 8192 RAMs of 32 bits or less.
26. What is retention algorithm for memories?
The retention program usually involves writing a checkerboard pattern to the memory, waiting for a pre-determined amount of time (the retention spec) and then going back to read the memory, making sure the contents did not change.
This algorithm can be included in a BIST implementation - the controller does the write, and then asserts a signal telling you that it is waiting. After the specified retention time, you assert a resume signal, and the contents are read back. You would then do this for the inverse data pattern.
27. What is D2 violation and how to solve?
Mentor ATPG - the D2 indicates a copy cell that gets the same data as an upstream flop in shift mode, and may or may not get the same data during capture. It's a violation when they get the same data during capture, I believe, and will reduce fault coverage. If you set split capture cycle on, it should be resolved (consult your tool docs, and it will tell you all this).
28. How to decide the number of Scan chains?
Number of package pins available for scan I/O,
Size of the design,
EDA tools available for use (w/ or w/o compression?),
The targeted ATE (available pin count and vector memory),
The test run time desired.
They're all inter-related, so you start usually with the first two, try to figure out whether or not you're going to fit on your targeted tester, and go from there - make the trade-offs...
29. How the compression technique factor affects the Number of scan chains? Is number of Clock domains also a factor?
Clock domains are a factor, yes, but sometimes people will combine clock domains into the same scan chain. That's not uncommon, and will work if the clock skew is managed, and the tool puts lockup latches in there.
Compression affects the number of scan chains, of course, since more compression generally uses fewer external scan chains.
30. What’s the procedure to generate pattern in TFT LOC Using Fastscan tool.
Shall i generate PI to CLk, CLK to CLK & CLk to po patterns seperately.
I would say that normally, you'd just create clock to clock patterns, not PI to clock and clock to PO (so just mask pi's and po's). The clock to clock are really the main objective of transition fault tests.
Ans: PBIST is the TI Internal IP used to test the memories in the design popularly called as Programmable BIST. As design is moved to deep micron, knowing the nature of defect is very challenge in silicon. Hence we want to have programmable BIST to support algorithms that have been developed post silicon.
Key feature:-
=========
1. It can able to support test 8192 memories in the design.
2. Ability to run different algorithm even post silicon.
3. Support ROM based testing.
Programmable Built-In Self-Test (PBIST) is a memory DFT feature that incorporates all the required test systems into the chip itself.
PBIST was originally adopted by large memory chips that have high pin counts and operate at high frequencies, thereby exceeding the capability of production testers. The purpose of PBIST is to avoid developing and buying more sophisticated and very expensive testers.
PBIST or programmable built-in Self Test is a technique of memory testing. The PBIST strategy, as the above responders have mentioned are basically the same as MBIST.
The difference lies in the architecture and the hierarchy.
For the PBIST, there is only a single BIST controller for a group of memories, as against one controller per memory type in MBIST. In PBIST, memories are grouped under different groups, and are treated as separate memory instances. Each memory instance is accessed by a unique RGS, RDS and CSR value. The RDS value selects the return data slice.
The PBIST controller can be accessed through 3 interfaces: VLCT (Very low cost tester), ROM and CPU. This VLCT interface makes the PBIST programmable during testing of the device, as against MBIST, where the algorithms are hard-coded and cannot be changed once fixed.
Elaborating the terms used in the above respond that will add further clarity to the concept:
RGS, RDS, CSR... etc all these are PBIST internal configuration registers used for PBIST programming. All the configuration registers are memory mapped for access by the CPU through the VBUS interface in all modes.
Chip Select Register - CSR[31:0]
PBIST implements a chip select of up to 32 RAMs with a 32-bit register. When a READ or WRITE command is executed, the corresponding Chip Select is driven active and enables that RAM. At reset, the default value of the register is all 0s.
CSR is normally the same as the 32-bit decoded value of the 5-bit RDS. For a memory to be selected, the corresponding CSR bit pointed to by the RDS register should be set to 1. More than 1 CSR could be turned on at the same time to excite more than one memory simultaneously, but the return data will always be selected from one memory pointed to by the unique RDS.
We have a 32 bit RAM Configuration Register (RAMT[31:0]) which is internally divided into 6 registers, none of which have a default value after reset.
RGS, RDS are part of RAMT.
RAM Group Select [7:0] (same as RAMT[31:24])
In order to support more than 32 RAMs, this RAM grouping address register has been provided. This extends the total number of RAMs that can be tested from 32 to 8192 RAMs of 32 bits or less. RAMs with data width larger than 32 will be tested as more than one RAM and data logged separately.
Return Data select [7:0] (same as RAMT[23:16])
This register is for selecting memory return data for selected RGS group. 8 bits of RGS and 5 bits of RDS give flexibility to test 8192 RAMs of 32 bits or less.
26. What is retention algorithm for memories?
The retention program usually involves writing a checkerboard pattern to the memory, waiting for a pre-determined amount of time (the retention spec) and then going back to read the memory, making sure the contents did not change.
This algorithm can be included in a BIST implementation - the controller does the write, and then asserts a signal telling you that it is waiting. After the specified retention time, you assert a resume signal, and the contents are read back. You would then do this for the inverse data pattern.
27. What is D2 violation and how to solve?
Mentor ATPG - the D2 indicates a copy cell that gets the same data as an upstream flop in shift mode, and may or may not get the same data during capture. It's a violation when they get the same data during capture, I believe, and will reduce fault coverage. If you set split capture cycle on, it should be resolved (consult your tool docs, and it will tell you all this).
28. How to decide the number of Scan chains?
Number of package pins available for scan I/O,
Size of the design,
EDA tools available for use (w/ or w/o compression?),
The targeted ATE (available pin count and vector memory),
The test run time desired.
They're all inter-related, so you start usually with the first two, try to figure out whether or not you're going to fit on your targeted tester, and go from there - make the trade-offs...
29. How the compression technique factor affects the Number of scan chains? Is number of Clock domains also a factor?
Clock domains are a factor, yes, but sometimes people will combine clock domains into the same scan chain. That's not uncommon, and will work if the clock skew is managed, and the tool puts lockup latches in there.
Compression affects the number of scan chains, of course, since more compression generally uses fewer external scan chains.
30. What’s the procedure to generate pattern in TFT LOC Using Fastscan tool.
Shall i generate PI to CLk, CLK to CLK & CLk to po patterns seperately.
I would say that normally, you'd just create clock to clock patterns, not PI to clock and clock to PO (so just mask pi's and po's). The clock to clock are really the main objective of transition fault tests.
