36. One thing I am not able to completely appreciate is whether there is an issue while sharing functional pin for testing. Does it in anyway reduce the coverage?
Not if it is handled properly. You need to ensure that a test mode exists where the functional paths to the shared I/O are accessible. For example, you may have a test mode where scan testing is performed with the shared I/O connected up to scan chains and a separate test mode with the shared I/O in their normal functional setting where they can be tested say with boundary scan.
37. what is the command to be used in RTL compiler to add a mux at the PI which, is used as a shared scan enable signal, with test_mode as its select
define_dft test_mode -name test_mode -active high TM
insert_dft test_point -location -type control_node -node scanenable -test_control test_mode
38. when doing DFT scan insertion which of the following is true or is a better approach?
1. Up to three additional pins are required to implement this type of scan. Only the SCAN ENABLE pin must be dedicated; the remainder of the pins(scan in, scan out) can be shared with primary inputs and outputs.
2. Up to four additional pins are required to implement this type of scan. Only the TEST MODE pin must be dedicated; the remainder of the pins(scan en, scan in , scan out) can be shared with primary inputs and outputs.
First you will of course generally use more than one scan chain and often need more than one scan enable (SE) signal, so your 3 and 4 pin statements don't really hold true. The real question you're asking is if the SE signal(s) must be dedicated or not or can a TM signal be used so that the SE signal can be shared. The answer is that a TM signal can indeed be used to share the SE signal(s). This is generally the prefered solution as very often the design requires other internal test settings which mush be controlled by a dedicated TM signal.
39. Why Full Scan is considered combinational?
Now what I think about is that one can control the sequential part by using the scan path. This is done by clocking in the needed sequence to set up the state of the machine and then applying the PIs (primary input vectors) to the combinational inputs.
Thus you one can easily see the response of the machine without having to go through the state machine in its originally specified way. Thus we become independent of the state machine in some way.
Thus using scan we 'reduce' the sequential machine problem down to a 'combinational' problem.
By definition, Full Scan means that ALL flip-flops in the design are converted into scan flops. When the scan-enable signal is inactive, the flip-flops accept data from their functional inputs and the circuit behaves in its intended sequential nature. When the scan-enable signal is active, all flip-flops accept data from their scan input, providing full control on the values that get loaded into them. In this mode, all sequential depth is removed leaving only a combinational circuit to test.
40. It is very normal in our designs to have multiple clock domains.
In that case do we create scan chain for each clock domain?
Also, is the scan clock different from normal clock used during normal functionality?
Are there issues in scan testing when the clock is generated internally (say using PLL)
Yeah.. we need to create seperate scan chains for each clock domain..
same clocks can be used as scan clocks as this will reduce extra pins.
After going through some theory on DFT, I found the following answers:
1) the functional clock is bypassed for scan testing. So clocks in multiple domains can be clubbed into a single chain with a single clock if DC testing is the only target
2) About the pll also, the answer is same since the internal clock is bypassed and scan clock is used, the pll remains inactive during scan testing
