DFT Q&A - Part 20

Ques : What are the thinks to be considered in scan stitching? I know little bit about this can you explain me more in details?

Ans : Scan stitching is done can be done in one of three ways:

1) Use the synthesis tool (DFT compiler or equivalent)
2) A DFT scan tool (such as DFT Architect)
3) The place and route tool

Some of the things to think about are:

1) How many scan ports do you have available? This will determine, in part, the number of scan chains. The scan chains need to be balanced in length to be as efficient as possible, for test-time/data volume.
2) Clocks - will you use flops from different clock domains in the same chain? If so, the clock domains need to be *reasonably* skew balanced for the chains to work properly. Also, lockup-latches will be necessary where the scan path crosses the clock domains for safe operation (if stitching.
3) Are there negative edge flops in the design? If so the tool will always place the negedge flops, as a group, ahead of the posedge flops.

Ques : why first negative edge flops followed by positive edge flops in the scan chain?

Ans : Well that's so the chain will shift data in and out properly. The idea is that each bit of the data shifting into the chain should traverse the chain one flop at a time.
Given a clock that is defined with an off-state of 0, a positive edge comes before a negative edge in time, right?
Now imagine in a scan chain, a posedge FF followed by a negedge FF. During any given clock period, the data that is latched into the posedge FF will also be latched into the negedge FF as well - in the same period. This is called a feed-through, and is generally not an optimal situation for the ATPG.
However, if the insertion tool puts the negedge flops all grouped at the front of the chain, then the boundary between the negede flops and posedge flops will be a negedge FF followed by a posedge FF. Since the positive edge of the clock comes before the negative edge, the data will be properly held up at the negedge FF until the next clock period.

Ques : Apart from the conventional mux FF scan architecture, there are many others like the Level Sensitive scan and the clocked scan etc. How are these better or worse than the muxed FF technique?

Ans : LSSD is really a sub-specialty in the industry as a whole only a few companies use it, but it is effective. For scan purposes, it does not suffer from the hold time issues that mux-scan normally does, but area-wise, it's not as good.
Clock-scan uses a separate scan-clock for each flop - I've never seen it used in industry, but that's just me. The problem with it is that you must route two clock trees around the chip instead of one - a virtual show-stopper in these days of congested routing.

Ques : By full scan methodology do we mean that every single flop in the design is a part of the scan chain? And if we have multiple scan chains instead of one, as it is in present designs, can it still be called full scan methodology?

Ans : In a perfect world, full scan means every flip-flop, but in the real world, many flops can be unscanned, and the design is still considered full scan. In some cases, the ATPG tool can test through unscanned flops without a major impact to fault coverage. Designs using one or many scan chains are equally valid as full scan designs.

Ques : What is a BUS Primitive and clock_PO pattern?

Ans : A bus primitive is just a DFT model of a bus - a net that has more than one driver. It's important that you constrain it during test.
A clock PO pattern is a pattern that measures a primary output that has connectivity to a clock. So if a clock signal propagates through combinational logic to a primary output (PO), an ATPG vector can be created to measure the results of that propagation

Ques : What is the difference between test pattern and test vector ?

Ans : The terms are sometimes used interchangeably. Me, I tend to say that a test pattern is a set of test vectors.
However, the ATPG tools generally give you stats that claim a certain number of 'patterns', but personally, I would call them 'vectors'.

Ques : During the process of ATPG, I encountered a term called clocked PO pattern. Could someone throw some light on what are these patterns ?

Ans : Clock PO patterns are special patterns meant to test primary output values when those primary outputs are connected, directly or indirectly, to one of the scan clocks (usually through combinational logic or just buffers).