Mentor Graphics announced the full interoperability between the Tessent IJTAG chip-level IP integration product and ASSET InterTech’s ScanWorks platform for embedded instruments, which includes chip, circuit board and system-level IJTAG tools.
This combination delivers a comprehensive chip-to-system-level automated IJTAG IP integration solution, greatly simplifying the user’s ability to leverage chip-level resources to the printed circuit board (PCB) or system levels.
Chip IP that is compliant with the IJTAG standard (IEEE P1687), such as self-test or diagnostic functions, can now be seamlessly accessed from board debug, validation and test systems or in the field from system software.
Tessent IJTAG combined with ScanWorks lets engineers access the operational and diagnostic features of all IP blocks in the design from a top-level interface, greatly simplifying the job of integrating the hundreds of IP blocks in a typical system. Interoperability between the two solutions revolves around the IEEE P1687 standard’s Instrument Connection Language (ICL) and Procedural Description Language (PDL).
The Tessent IJTAG tool reads ICL and PDL code delivered with third-party IP blocks and verifies that it is IEEE P1687 (IJTAG)-compliant. It then generates a logic network and associated ICL to integrate all the IP blocks in a design and processes the PDL for each IP to create composite chip-level PDL. The ScanWorks product then reads chip-level ICL and PDL for use in chip debug and also retargets the PDL to a board or system level interface.
Chip IP that is compliant with the IJTAG standard (IEEE P1687), such as self-test or diagnostic functions, can now be seamlessly accessed from board debug, validation and test systems or in the field from system software.
Tessent IJTAG combined with ScanWorks lets engineers access the operational and diagnostic features of all IP blocks in the design from a top-level interface, greatly simplifying the job of integrating the hundreds of IP blocks in a typical system. Interoperability between the two solutions revolves around the IEEE P1687 standard’s Instrument Connection Language (ICL) and Procedural Description Language (PDL).
The Tessent IJTAG tool reads ICL and PDL code delivered with third-party IP blocks and verifies that it is IEEE P1687 (IJTAG)-compliant. It then generates a logic network and associated ICL to integrate all the IP blocks in a design and processes the PDL for each IP to create composite chip-level PDL. The ScanWorks product then reads chip-level ICL and PDL for use in chip debug and also retargets the PDL to a board or system level interface.
