Routing process determines the precise paths for nets on
the chip layout to interconnect the pins on the circuit blocks. Before
discussing further, it would be prudent to discuss where does Routing actually fit in the Physical Design flow.
After Synthesis (the conversion of RTL to gate-level netlist), the blocks and the instances are Placed, which, to some extent, is governed by the Floorplan. After Placement, Clock Tree is synthesized followed by Routing of the signal nets. The following flow chart summarizes the Physical Design Flow.
Routing is further divided into many subtypes:
Objectives of the Routing Process:
- To determine the necessary wiring, e.g., net topologies and specific routing segments, to connect these cells while respecting constraints like design rules.
- To Optimize routing objectives, e.g., minimizing total wire length and maximizing timing slack.
Routing is further divided into many subtypes:
- Global Routing: It defines the routing regions and generates a tentative route for each net. Each net is assigned to a set of routing regions. However, it does not specify the actual layout of wires and it not sensitive to DRV violations.
- Detailed Routing: For each routing region (defined during Global Routing), each net passing through that region is assigned to particular routing tracks. The actual layout of wires is specified. It also tries to fix all DRV violations in the design.
