Lock-Up Latches are important elements for any STA engineer while
closing timing on their DFT Modes: specially the Hold Timing Closure of
the Shift Mode. While shifting, the scan chains come into picture, which
are nothing but the chains of Flops involving the output pin of one
flop, connected to the Scan-Input or Test-Input pin of the other flop,
and so on, forming a chain.
Now, imagine that we have two functionally asynchronous domains 1 and
2. Functionally asynchronous means that during the normal mode of
operation (Functional Mode), the two domains do not interact with each
other. However, very rarely do the designers have the liberty to make a
separate scan chain for functionally asynchronous domains. Let's
consider the following scenario: where domain 1 has the average clock
latency of 3ns, and domain 2 has the average latency of 6ns. And the
time period of the test clock is, let's say, 10ns.
Now, let's see the timing checks for this scenario. The output of the
last flop of the domain 1 is in scan-chain and connected to the
Test-Enable input of the first flop of domain 2. The check would be
like:
Owing to the positive clock skew, the setup check would be relaxed,
but hold would be critical. Two possible options to fix the hold timing:
- Insert the buffers, to add sufficient delay, so that hold is finally met.
- To add the Lock-Up Latch between the two flops where scan chain crosses the functional domains.
The first might not be a robust solution because the delay of the
buffers would vary across the PVT Corners and RC Corners. In the worse
case, there might be a significant variation in the delays across
corners and you might witness closure of timing in one corner, but
violation in other corner!
Second solution is a more robust solution because it obviates the above scenario. Hence see how it does it.
Timing Check would be like:
Hence, both setup and hold checks are relaxed!!
[Please note that in the above circuit, the latch is a negative level triggered latch.]
