Power consumption is a growing concern for modern SoCs and design
engineers today face an arduous task of limiting the power dissipation
of their SoCs. It would be unfair to think the backend design cycle as a
magical solution to all the power solutions. However, modern synthesis
EDA tools are smart enough in identifying some key RTL constructs and
synthesizing a low power equivalent of the structure. We will take a
look at one such RTL Construct and it's equivalent implementation for
low power design.
Consider the following behavioral description:
always @ ( posedge clk )
begin
if (enable == 1'b1) then
q [15:0] <= d [15:0]
end
One logical implementation and the corresponding low power implementation of the above description would be:
The synthesis tools find such RTL constructs and try and convert it into the low power implementation shown above. Please note that, the clock gating integrated cell (CGIC) also consumes power and the above implementation might not be an expedient solution if the above enable is mostly high, or even if the number of registers in the register set is small. Therefore, one needs to exercise caution while using or implementing such a structure!
Consider the following behavioral description:
always @ ( posedge clk )
begin
if (enable == 1'b1) then
q [15:0] <= d [15:0]
end
One logical implementation and the corresponding low power implementation of the above description would be:
The synthesis tools find such RTL constructs and try and convert it into the low power implementation shown above. Please note that, the clock gating integrated cell (CGIC) also consumes power and the above implementation might not be an expedient solution if the above enable is mostly high, or even if the number of registers in the register set is small. Therefore, one needs to exercise caution while using or implementing such a structure!
