Timing Violation can manifest due to a plethora of reasons. And it is
important for an STA Engineer to understand the violating path and
model the constraints properly before providing them to the
Synthesis/PnR tools for optimization. Unnecessary optimization should be
avoided because:
- To save on the die area;
- To save on the leakage power;
- To prevent unnecessary congestion.
The figure below shows a scenario. Assume the clock period to be 8ns
and the setup time of the capture flop (here, FF3) be 0ns and the
clock-to-Q delay of the launch flops (here, FF1 & FF2) be 0ns. The
violating path is shown in the figure. The negative slack is 1ns.
How would you fix the above violation? Please note that there are
many possible solutions; but one only solution adheres to the above
discussed constraints of leakage power, area and congestion.
