DFT Q&A - Part 9

56. I need to know how to implement simulation about Bridge faults?

I mean is the same way like stuck simulation (for example to activation the stuck line with the opposite value) If no, then how to do the simulation?

For bridging fault simulation, there are two things that are different from stuck-at:

1. Bridging fault list

2. Bridging fault behavior

It is impossible to use all pairs of nets/nodes in the gate level netlist as a bridging fault list in practical circuits, so people typically extract physically adjacent nets (with perhaps some minimum length of adjacency) to be fault sites. In absence of physical information, some folks tried logical proximity with varied degrees of success.

When two nets are bridged together, and the two nets were driven to different logic levels, the result logic depends on:

1. The drive strength of the cells driving the 2 bridged nets

2. The bridge resistance

3. The logic threshold of the cells inputs driven by the bridged nets

Some simplistic models that are often used to model the faulty behavior are wired-AND, wired-OR, A-dominate, B-dominate, or some other combination of these models.

You can read more about this in the following paper:

"A Comparison of Bridging Fault Simulation Methods", ITC 1999.

http://ieeexplore.ieee.org/xpls/abs_all ... ber=805783

57. what is the difference between sequential and combinational atpg?

Combinational ATPG simulate one clock pulse on the circuit. Sequential ATPG simulate multiple pulses.

58. What is parallel scan chain loading for simulation? Do we force scan in values for parallel loading? How it works? How it is different from serial loading?

parallel scan chain loading means forcing the scan in port of the flops parallely.

serial loading means Serial shift register. first serially shift in the values into the registers by pulsing the clocks(no of flops)

When running atpg pattern on to a scan inserted netlist in a commerical testing tools. Is there any I can find out which atpg pattern is sent into which scan chain of the scan-netlist.

When dealing with test data compression, it's hard to know exactly which chain is being tested at any one time. Some tools may be able to report which chain(s) are tested for a given pattern, but then the answer may come back that several chains were being tested at once.

It would be different for straight-ahead scan, because you know exactly what path the data takes as it goes in and comes out of the scan chains.

59. How does "scan compression logic (XPAND + X-Compact)" work ? Can it generate any arbitrary test vector ?

Both XPAND and X-Compact techniques are based on combinational logic( XOR gate). It can use test patterns generated from any atpg tool. XPAND works on Illinois scan idea. The problem is that when there are X's present at the X-Compact end, test coverage gets reduced.

Reference:

[1] Subhasish Mitra, Kee Sup Kim, " XPAND: An Efficient Test Stimulus Compression Techniques", IEEE Transactions on Computers, vol 55, pp 163 -173, Feb 2006.

[2] Subhasish Mitra, Kee Sup Kim, " X-Compact: An Efficient Response Compaction Technique", IEEE Transactions on CAD of Circuits and Systems, Vol 23, pp 421-432, March 2004.

60. During the process of ATPG, I encountered a term called clocked PO pattern. Could someone throw some light on what are these patterns ?

Clock PO patterns are special patterns meant to test primary output values when those primary outputs are connected, directly or indirectly, to one of the scan clocks (usually through combinational logic or just buffers).