16. What is stuck open kind of memory fault?
Ans: Stuck open fault in memory says that a particular memory cell is not accessible. A single physical line in a circuit may be broken. The resulting unconnected node is not tied to either VCC or Gnd.
In the figure, if A=1 & B=0, then there is no path from either VDD or VSS to the output F. The output F retains its previous value for some undetermined discharge time.
17. In my project we have 3 subchips. We have three DFT modes of operation. In each mode all the pins of particular subchip will be accessible from Top level. During pattern generation I am facing chain blockage at scan cell 0 for one particular mode. Please help me in debugging the issue.
Ans: There can be many reason for this.
1. The design that you are using might not be Scan Stitched.
2. You might not have declared the Clock
3. The asynchronous reset might not be constrained during shift procedure in your spf file (TETRAMAX) or procedure file (Fastscan)
4. You might not have given proper constraints to input pins
5. Improper value of some dft mode control signals
For finding the exact issue. you have to analyze the error using the gui/schematic viewer of the tool
case 1 : You will find Q of the flop shorted with the SD of the same flop
case 2 : X at the clock port of the flop
case 3 : X at the reset port
case4 : You might see more than one input of a gate as X ; hence the tool will not know which path to follow
Case5 : you might see more than one input of a gate as X; hence the tool will not know which path to follow
Please check the I/O buffer which is used on the scan out is in output mode. else there will be a blockage at the scan cell 0. Make sure that all the I/Os on the scan out port are in the output mode and all your scan-in pins in input mode.
Check the two things first,
1. the flop where it is blocked, there clock is coming properly or not
2. Reset for the same flop
18. For my design i generated the atspeed compressed patterns. when i simulated these patterns serially then all of them were passing. i deleivered these patterns( in wgl format) to our tester team. they sent me the scan tool data and asked me y they are getting these errors. some of the errors from that log file are shown below
err nbr|cycle number|pinname|template |inst |nrmoff|frames |registers |E|R
1| 32171 |LCD_D16 |st_0_577 | 49| 35 |LCD_D160| |1|0
2| 49596 |LCD_D16 |st_0_577 | 79| 40 |LCD_D160| |1|0
i tried to debug this problem using cycle based log method of tetramax . but i dint able to figure out the exact flop. i came to know that for debugging compressed patterns through this method or through failpattern log based method first i need to convert these adaptive scan patterns to basic scan patterns then only i can debug them.
do we have any other method to debug the compressed patterns?
is inst show scan chain number and nrmoff show the failing flop position?
Ans: various pattern generation tool provides diagnostic capability to debug the Compressed patterns, but there is a restriction based on the no of channels used at the top level and the compression factor defined while inserting the compression logic.
It is better to convert those patterns into basic patterns and do a parallel simulation, which is a easier way to debug the failures. Parallel simulation is faster and easier to debug. Tool provides the flop name, number and also the chain number too.
19. On what basis do we select LOS or LOC in DFT? Is there any major run time difference too in the execution of these two concepts?
Ans: It is necessary that the timing path should be same as the functional path. i.e., clocks should be the same in both functional & at-speed test mode. Whatever methodology (Launch On Shift / Launch On Capture) is required to meet this requirement should be implemented. There are other critical factors that will also drive to LOS / LOC implementation.
1. Whether clocks are generated by internal PLLs.
2. Whether, tester can support multiple waveforms on the same clock pin.
3. How do you handle scan enable to switch between shift & capture modes.
FYI, most of the designs that have internal clock generators implement LOC method for testing.
Below are differences between the LOC and LOS
a) For LOS the scan enable has to closed at functional frequency (which may result in gate count increase with addition of large buffers), whereas in LOC the timing on scan enable can relaxed between the last shift and launch cycle.
b) LOS atpg run time is less compared to the LOC for pattern generation.
c) Pattern count in LOS in less than the LOC.
d) Test/fault coverage for LOS is higher than the LOC.
Transition ATPG is meant for detecting slow-to-rise and slow-to-fall faults on a particular node. In order to detect the transition fault, we have to create the transition on the node. We can achieve this in two ways
I) Launch on last shift - In this method, during the last shift itself, we will shift in the required value in to the flop which will create the required transition on the intended node.
Advantages: 1) Tool has the controllability to put the required value in to the flop
to cause transition.
2) We will get good coverage as we are launching the value through
SD path.
Disadvantages: 1) Scan-enable need to change at-speed, we have to implement
pipeline logic in order to support this.
II) Launch on capture - In this method, the flop which creates the launch on the intended node will get the value through D path. Scan-enable will be low during this time.
Advantages: 1) No need to add pipeline logic for Scan-enable.
Disadvantages: 1) We may loose some coverage as the value is launched through D
path.
Its always better to go with LOS, The major advantage with LOS is increased coverage and reduction in number of patterns. When the no of patterns decreases, the test time reduces, which in turn reduces the cost for test time to a great extend.
20. In my project I am facing failures in TDL simulation. I have loaded the failing flops signals in the waveform viewer. This is chain TDL in which scan enable is always 1. Q output should follow the SI input. Whenever there is change in SI input Q should change at next clock edge. But I am seeing Q output is changing at the same clock edge when the SI changes. Only for two flops I am seeing this kind of behaviour. All other flops it is working fine.
Can anyone tell me why this behavior is happening. Please let me know anybody has faced this kind of issue.
Ans: The output of the flop should have certain clk to q delay. even in notiming models (this is done to take care of delta delay issues in rtl simulation)
now in ur case : the clock to the two flops (source and destination) may be comming at two different time. This will happen when we knowingly delay the clk to avoid delta delay issue.
Check the clk path to see if both clocks are arriving at same time or not (ideally they should come at same time) if u are using single scan clock for all flops.
When you do zero-delay simulations, the library files used should be supporting this.
If the library model is based on the udp cell definition, then it is more susceptible to race conditions as described by you. There are two options to get rid of this.
1) Use always blocks to define the flip-flop behavior. Use this model instead of the normal library model.
2) Modify the library model to have internal delay for the d and sdi signals.
21. What is the difference between coverage from dft max and coverage from tetramax?
Ans: DFTMAX is a method or a module which is used to implement compressed mode. Compressed mode means we externally we might have say 8 scan chain (8 scan in port and 8 scan out ports) but DFTMAX translate it into say 240 chains internally. The DFTMAX module will have a demux 8 to 240 and a mux 240 to 8.
This will reduce test time. as the shift time reduce by a factor of 30. This will have lower coverage numbers by a small amount. Since we are loosing certain amount of uncontrollablity as well as observability due to increased effort of the tool.
you can make up this coverage loss by loading the dftmax fault list and running a normal non compressed scheme.
TETRAMAX is a tool which is used to generate patterns. for both compressed and non compressed mode/scheme.
22. Can anybody please tell me what tester cycle is?
Can it be less than Scan clock period or capture clock period?
Ans: A tester cycle refers to the reference clock for the tester. It should be the fastest clock for any test pattern.
For a scan pattern, the tester clock can be faster than the scan clock. If clock is driven like a data pin (using NRZ) from the tester, a scan clock period is equal to 3 tester clock cycles (Refer to the waveform table for scan clock that says 0ns D, 50ns U, 80ns D).
23. What is the difference between BIST and NON-BIST tdls?
Ans: 1. BIST : Built In Self Test.
- MBIST/PBIST
- LBIST
Chip will test by itself using BIST. If you say BIST TDL, it will have programming sequence / seed to generate patterns internally from BIST instead from tester.
2. Non-BIST:-
- EDT
- DFTMAX
These TDL's are having test vectors which will be driven from tester to chip.
24. Why first negative edge flops followed by positive edge flops in the scan chain?
Ans: This is not necessary to always have negative and positive edge triggerred flops in scan chain. Actually we can have three combinations:
1) All positive
2) All negative
3) Negative followed by positive
but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not possible. We will require lock up latch.
The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge then you a lock up latch (if skew is small)
this depends on the nature of clock involved in your scan design.
Clock nature
1 : RTZ then chain should be : negedge ->posedge
2 : non RTZ thene it shoul be vice-versa
reason is value loaded on first flop shhuld not passed on to next FF in same cycle.
Ans: Stuck open fault in memory says that a particular memory cell is not accessible. A single physical line in a circuit may be broken. The resulting unconnected node is not tied to either VCC or Gnd.
In the figure, if A=1 & B=0, then there is no path from either VDD or VSS to the output F. The output F retains its previous value for some undetermined discharge time.
17. In my project we have 3 subchips. We have three DFT modes of operation. In each mode all the pins of particular subchip will be accessible from Top level. During pattern generation I am facing chain blockage at scan cell 0 for one particular mode. Please help me in debugging the issue.
Ans: There can be many reason for this.
1. The design that you are using might not be Scan Stitched.
2. You might not have declared the Clock
3. The asynchronous reset might not be constrained during shift procedure in your spf file (TETRAMAX) or procedure file (Fastscan)
4. You might not have given proper constraints to input pins
5. Improper value of some dft mode control signals
For finding the exact issue. you have to analyze the error using the gui/schematic viewer of the tool
case 1 : You will find Q of the flop shorted with the SD of the same flop
case 2 : X at the clock port of the flop
case 3 : X at the reset port
case4 : You might see more than one input of a gate as X ; hence the tool will not know which path to follow
Case5 : you might see more than one input of a gate as X; hence the tool will not know which path to follow
Please check the I/O buffer which is used on the scan out is in output mode. else there will be a blockage at the scan cell 0. Make sure that all the I/Os on the scan out port are in the output mode and all your scan-in pins in input mode.
Check the two things first,
1. the flop where it is blocked, there clock is coming properly or not
2. Reset for the same flop
18. For my design i generated the atspeed compressed patterns. when i simulated these patterns serially then all of them were passing. i deleivered these patterns( in wgl format) to our tester team. they sent me the scan tool data and asked me y they are getting these errors. some of the errors from that log file are shown below
err nbr|cycle number|pinname|template |inst |nrmoff|frames |registers |E|R
1| 32171 |LCD_D16 |st_0_577 | 49| 35 |LCD_D160| |1|0
2| 49596 |LCD_D16 |st_0_577 | 79| 40 |LCD_D160| |1|0
i tried to debug this problem using cycle based log method of tetramax . but i dint able to figure out the exact flop. i came to know that for debugging compressed patterns through this method or through failpattern log based method first i need to convert these adaptive scan patterns to basic scan patterns then only i can debug them.
do we have any other method to debug the compressed patterns?
is inst show scan chain number and nrmoff show the failing flop position?
Ans: various pattern generation tool provides diagnostic capability to debug the Compressed patterns, but there is a restriction based on the no of channels used at the top level and the compression factor defined while inserting the compression logic.
It is better to convert those patterns into basic patterns and do a parallel simulation, which is a easier way to debug the failures. Parallel simulation is faster and easier to debug. Tool provides the flop name, number and also the chain number too.
19. On what basis do we select LOS or LOC in DFT? Is there any major run time difference too in the execution of these two concepts?
Ans: It is necessary that the timing path should be same as the functional path. i.e., clocks should be the same in both functional & at-speed test mode. Whatever methodology (Launch On Shift / Launch On Capture) is required to meet this requirement should be implemented. There are other critical factors that will also drive to LOS / LOC implementation.
1. Whether clocks are generated by internal PLLs.
2. Whether, tester can support multiple waveforms on the same clock pin.
3. How do you handle scan enable to switch between shift & capture modes.
FYI, most of the designs that have internal clock generators implement LOC method for testing.
Below are differences between the LOC and LOS
a) For LOS the scan enable has to closed at functional frequency (which may result in gate count increase with addition of large buffers), whereas in LOC the timing on scan enable can relaxed between the last shift and launch cycle.
b) LOS atpg run time is less compared to the LOC for pattern generation.
c) Pattern count in LOS in less than the LOC.
d) Test/fault coverage for LOS is higher than the LOC.
Transition ATPG is meant for detecting slow-to-rise and slow-to-fall faults on a particular node. In order to detect the transition fault, we have to create the transition on the node. We can achieve this in two ways
I) Launch on last shift - In this method, during the last shift itself, we will shift in the required value in to the flop which will create the required transition on the intended node.
Advantages: 1) Tool has the controllability to put the required value in to the flop
to cause transition.
2) We will get good coverage as we are launching the value through
SD path.
Disadvantages: 1) Scan-enable need to change at-speed, we have to implement
pipeline logic in order to support this.
II) Launch on capture - In this method, the flop which creates the launch on the intended node will get the value through D path. Scan-enable will be low during this time.
Advantages: 1) No need to add pipeline logic for Scan-enable.
Disadvantages: 1) We may loose some coverage as the value is launched through D
path.
Its always better to go with LOS, The major advantage with LOS is increased coverage and reduction in number of patterns. When the no of patterns decreases, the test time reduces, which in turn reduces the cost for test time to a great extend.
20. In my project I am facing failures in TDL simulation. I have loaded the failing flops signals in the waveform viewer. This is chain TDL in which scan enable is always 1. Q output should follow the SI input. Whenever there is change in SI input Q should change at next clock edge. But I am seeing Q output is changing at the same clock edge when the SI changes. Only for two flops I am seeing this kind of behaviour. All other flops it is working fine.
Can anyone tell me why this behavior is happening. Please let me know anybody has faced this kind of issue.
Ans: The output of the flop should have certain clk to q delay. even in notiming models (this is done to take care of delta delay issues in rtl simulation)
now in ur case : the clock to the two flops (source and destination) may be comming at two different time. This will happen when we knowingly delay the clk to avoid delta delay issue.
Check the clk path to see if both clocks are arriving at same time or not (ideally they should come at same time) if u are using single scan clock for all flops.
When you do zero-delay simulations, the library files used should be supporting this.
If the library model is based on the udp cell definition, then it is more susceptible to race conditions as described by you. There are two options to get rid of this.
1) Use always blocks to define the flip-flop behavior. Use this model instead of the normal library model.
2) Modify the library model to have internal delay for the d and sdi signals.
21. What is the difference between coverage from dft max and coverage from tetramax?
Ans: DFTMAX is a method or a module which is used to implement compressed mode. Compressed mode means we externally we might have say 8 scan chain (8 scan in port and 8 scan out ports) but DFTMAX translate it into say 240 chains internally. The DFTMAX module will have a demux 8 to 240 and a mux 240 to 8.
This will reduce test time. as the shift time reduce by a factor of 30. This will have lower coverage numbers by a small amount. Since we are loosing certain amount of uncontrollablity as well as observability due to increased effort of the tool.
you can make up this coverage loss by loading the dftmax fault list and running a normal non compressed scheme.
TETRAMAX is a tool which is used to generate patterns. for both compressed and non compressed mode/scheme.
22. Can anybody please tell me what tester cycle is?
Can it be less than Scan clock period or capture clock period?
Ans: A tester cycle refers to the reference clock for the tester. It should be the fastest clock for any test pattern.
For a scan pattern, the tester clock can be faster than the scan clock. If clock is driven like a data pin (using NRZ) from the tester, a scan clock period is equal to 3 tester clock cycles (Refer to the waveform table for scan clock that says 0ns D, 50ns U, 80ns D).
23. What is the difference between BIST and NON-BIST tdls?
Ans: 1. BIST : Built In Self Test.
- MBIST/PBIST
- LBIST
Chip will test by itself using BIST. If you say BIST TDL, it will have programming sequence / seed to generate patterns internally from BIST instead from tester.
2. Non-BIST:-
- EDT
- DFTMAX
These TDL's are having test vectors which will be driven from tester to chip.
24. Why first negative edge flops followed by positive edge flops in the scan chain?
Ans: This is not necessary to always have negative and positive edge triggerred flops in scan chain. Actually we can have three combinations:
1) All positive
2) All negative
3) Negative followed by positive
but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not possible. We will require lock up latch.
The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge then you a lock up latch (if skew is small)
this depends on the nature of clock involved in your scan design.
Clock nature
1 : RTZ then chain should be : negedge ->posedge
2 : non RTZ thene it shoul be vice-versa
reason is value loaded on first flop shhuld not passed on to next FF in same cycle.
