DFT Q&A - Part 14

80. C6 violation during ATPG

set clock_off simulation on

set split capture_cycle on

And if the two commands does not resolve these issue, then you need to mask these flops.

Normally such violation occurs when Clock is seen as Data by ATPG tool.

For Fastscan the commands would be :

add cell constraint -drc C6

This will add constraint DX on the output of such registers.

What do you mean by typical scan frequencies?

Typical scan frequency is the frequency that most of the ATE's use when scanning in the data to the scan flops. it is typically around 1-10 Mhz.

Why is Hold time neglected while calculating Max Frequency?

To calculate the maximum frequency of the digital circuit, you will use the following
formula.

tCLOCK=tCHQV+tPD(max)+tSETUP.

Here, in all FFs, normally tHOLD < tCHQV, means Clock to Q output delay includes the hold time. So we are not considering the hold time for calculating the max. Frequency.

 In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves?

For designs with both positive and negative clocked flops, the scan insertion tool will always route the scan chain so that the negative clocked flops come before the positive edge flops in the chain. This avoids the need of lockup latch.

For the same clock domain the negedge flops will always capture the data just captured into the posedge flops on the posedge of the clock.

For the multiple clock domains, it all depends upon how the clock trees are balanced. If the clock domains are completely asynchronous, ATPG has to mask the receiving flops

 Why we avoid latches in the design, even if they provide only cell delay.
Is there any time related issues??  

Whenever latch is enabled it will pass whatever is there on its D inputs to Q output. If suppose any glitch is coming on D and latch is enabled it will pass it to q. Glitch always create problem u would be knowing this.

Latches are fast, consumes less power, less area than Flops but Glitches can also come along with these advantages, that’s why we go for flops.

Also Latches are not DFT friendly... It is very difficult to perform Static timing analysis with latches in your design...

While attempting to do scan insertion for a design, I am finding many uncontrollable clock and uncontrollable asynchronous signals like set and reset violations.
Can anyone guide me on how to avoid these violations?

Uncontrollable clocks are those which come out from a combo logic (dividers  ...etc)
when doing DFT, all the controls of the FF must be with respect  to the TEST EN signal,
in the sense once if TEST EN =1, then automatically the entire chip should be in scan mode .... for this all the clock of the FF should be controllable externally ( at pin level).

wherever u get a "uncontrollable clock" or uncontrollable set-reset please do the following
1) MUX the functional CLK with the "test clock" with the TEST EN as the select line and then give the o/p of mux as the input to the FF ( so that when TEST EN =1, the test clock will be given to all the FF and when TEST EN=0, the chip functions with normal clock )

What is the difference between a latch and a flip-flop?

• Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.

• They both are hence referred as "sequential" elements.

• In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably.

• In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.

• A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.

• Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

• Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.

• A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)

• A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.

• Latches are faster, flip flops are slower.

• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.

• Latches take fewer gates (less power) to implement than flip-flops.

• D-FF is built from two latches. They are in master slave configuration.

• Latch may be clocked or clock less. But flip flop is always clocked.

• For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.

Synthesis perspective: Pros and Cons of Latches and Flip Flops

• In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:"if" and "case" statements. This should be avoided sa latches are more prone to glitches.

• Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .

• Latch facilitates time borrowing or cycle stealing whereas flip flops allows synchronous logic.

• Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable" and "scan_enable" signals as input and feed the output to the enable port of the latch. [ref]

• Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e. triggered by the active time of clock, not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.

• If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which are prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool! This will create endless problems for the design team.

• Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch.
• Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

What do you mean by scan chain reordering?

Answer1: Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it.... it maintains the number of flops in a chain.

Answer2: During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion.

This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains.

Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.

What is software reset and hardware reset?

Software reset is a reset managed by software by writing a special register bit dedicated for this purpose; it's usually a synchronous reset.

Hardware reset is the traditional reset activated by setting the IC reset pin to '1' or '0' (depending on the convention: active low or active high reset), it can be also generated inside the IC.

In a Design which type of RESET (asyn or syn) will you prefer??

Best Solution is "Assert RESET asynchronously and De-assert Synchronously"

Active Low or Active HIGH?
If active high reset is used, any noise on the reset line can cause a spike and these results in a reset. But if active Low reset is used, this can never happen. So active low is preferred. This is the case where the reset comes from external to chip, but if reset is internally generated; then this may not be big issue.

Power point of view:
In cases where leakage is significant, active Low reset causes more leakage; as in in-active state the reset is active high and the transistor can leak slowly from high causing more leakage. So active high is preferred for low power.