Ques:- Suggest the design techniques for improving the testability?
Ans:
Prevention is better than Cure...
The above saying tells everything related to this information.
The scan design or design-for-testability (DFT) has been a standard in ASIC design flow for most designers, Obtaining high fault coverage for a design depends on the quality of the implemented DFT logic, and most \real-world" designs suffer from a variety of DFT related issues, which if left unsolved, result in reduced fault coverage. Designs with gated clocks and resets may not be good for testing, but the design style is used frequently. Since the clock pins of scan cells with gated clocks are not controlled by the primary input clock ports, a scan test is impossible without repair. The situation is the same for gated resets. Repair has been performed by inserting an additional primary input port `test-mode' and test logic in order to feed the top level clock (or reset) signal to the scan cells. This modication results in untestable faults due to the DFT constraints on the `test-mode' port, which lowers fault coverage.
There are some common reasons due to which we generally observe DRC violations. Here I am discussing those common areas and possible fixes if they are un-avoidable reasons.
In order to ensure a successful scan-based design (i.e., achieve high fault coverage), one must design with testability in mind throughout the design process. If the designer is aware of design structures that can derail testing efforts, he or she can adopt alternative design techniques whenever possible.
One of the bigest hurdle in system on chip (SOC) with respect to ATPG is controlling the internal tristate bus structures.
Bus contention occurs when two drivers are driving different values on the same bus. Since bus contention causes severe damage to the chip, it is important to prevent bus conflicts during normal operation as well as during scan. So, one should handle internal tristates with care and avoid bus contention by design.
In most designs, a bus has more than one driver. To avoid bus contention in normal operation, designers must make sure only one tristate gate at a time is selected. To satisfy testability rules, designers must set the signals for the bus drivers so that contention is eliminated in the test phase.
I can't say do not design internal tristate bus structures bus structures. But, I can suggest, if possible, never implement designs with internal tristate bus structures. If you can’t follow this rule, then implement the fewest possible internal tristate-bus structures and guarantee by design that no bus contention can occur on any internal bus during scan
testing.
Be careful of two important while handling contention issues.
1.Ensure that there is no contention on the tristate buses during scan-shift operations.
2. ensure that there is no possible contention on the internal tristate buses during the capture cycles during scan testing.
Most of the DFT tools are intelligent enough to take care of internal tri state buses during test logic insertion and will made proper fixes. And, some fixes has to be made manually. Even most of the ATPG tools will warn about the bus-contentions. Ultimately, test engineer has to take decision whether to generate the vectors that cause contention or to avoid it.
It is suggestable to avoid it or fully-decode the busses else, it may effect the chip productivity.
Gated clocks are generally used as one
of the power saving techniques. These clocks fan-in through at least one
combinational gate apart of buffers and inverters. Enable signal of the gated
clocks makes the followed sequential elemets in ON/OFF states. Unfortunately,
if the clocks of these flip-flops cannot be controlled from primary inputs,
these gated clocks make it impossible to scan in data. Removing these
flip-flops from the scan chain is one solution, but this results in a loss of
fault coverage.
One can employ one of the following
solutions as per the design and/or requirements.
Solution-1 is just excluding DFF from
the scan chain. This solution costs test coverage loss.
In Solution-2 the “Scan Mode” input
controls a multiplexer that changes/bypass the clock source for DFF. In this
case, output of AND gate is un-observable and all faults into the AND gate are
ATPG un-testable. To overcome this situation, one can add test-point at the
output of AND gate as shown below. By adding this logic to the solution-2
provide better ATPG test coverage.
3. Bypass Pulse generators and internally generated clocks
Here comes the internally generated
clocks/pulse generators (PLLs, frequency dividers, pulse generators). Before
going into the topic, I strongly suggest that DFT Engineer should always
question him/her self that whether he/she can control a particular internal
logic element via. primary inputs or not. It not add test logic to
control that element through primary inputs. Here the thumb rule is that the
primary inputs (scan clocks, reset etc.) should be controllable from any
primary input. Derived clocks can render a large part of the design untestable
because the flip-flops are not controllable from any primary input.
So, do not use clock dividers in ATPG
test mode. If your design contains clock dividers, bypass them in ATPG test
mode. Use the Scan Mode signal to control the source of the internal clocks, so
that in ATPG test mode you can bypass the clock divider and source the internal
clocks from the primary CLK output.
On the bottom line, do not use
phase-locked loops (PLLs) as clock sources and bypass the clocks while in ATPG
test mode.For pulse generators in the design, one can disable the pulse
generators by adding disabling logic or can bypass the pulse generator output
with access from a top-level input port as mentioned below.
4.
Asynchronous Set/Reset Signals
It is strongly recommended to avoid
asynchronous resets in the design. If it is unavoidable one can go ahead with
it bearing some test coverage loss. There are different ways to handle
asynchronous resets during test logic insertion to get a better test coverage.
There are different situations
generally one would face with reset signals.
1.Reset used as data:
In general, reset signal goes to the
reset pin of the sequential elements. We discuss in the next point what if the
reset is asynchronous reset. In some designs, reset is used as data. i.e. Reset
pin goes to the data input of the sequential elements. In such situations,
there are two different ways to handle this.
Option-1:
Option-2:
This is very tricky job. It is just to
play with the reset signal making it either active high or active low based on
the type of flops (active high or active low reset).
Assume, flops have active high reset.
During Shift Mode:
Control the reset signal fed to the
flop such that it is active low and keep the scan flop in the
active state. And the operation follows the regular scan operation where the
data is first shifted into the scan flip-flops holding at active low.
During Hold & Capture Mode:
In this case the vectors are generated
without applying any clocks during the capture operation, and the logic feeding
into the SET/RESET inputs (the Asynchronous path) of the scan flip-flops is
tested. The operation follows the regular scan operation where the data is
first shifted into the scan flip-flops holding at active state. Then during
hold and capture, de-activate those scan flops by proper controlling of the
reset signal fed into it. so that the signals are allowed to propagate through
the reset logic and modify the values in the scan flip-flops. Finally the results
are shifted out for comparison on the tester. This second option will improve
the test coverage either.
Below figure shows you how to control
the asynchronous reset signal fed into the flops.
Place an OR gate with one input as Scan
Enable signal and the other input of OR gate is the async. reset signal fanout
from the reset logic. One can use a dedicated signal in place of the Scan
Enable signal.
This method provides control to disable
asynchronous resets during scan shift only. The method makes the reset
controllable and will detect faults on the asynchronous reset of all registers
as well as test the reset logic circuitry. The only disadvantage of this
method is that the asynchronous resets will always be controlled by the
internal logic and can't be disabled during scan capture. This could cause
unwanted resets while attempting to test for other faults. As explained above,
one can avoid these unwanted resets by using a dedicated external signal to
control the disabling of the asynchronous resets during shift instead of using
the main ScanEnable signal.
Note: To follow the 2nd option, one
should be familiar with the corresponding tool command flow on which ATPG
vectors are generating. All most all the ATPG tools will have a proper command
flow to handle the asynchronous resets.
5.
Avoid Cross coupled Gates
In some designs, one can observe SR
latches. Though they are in expensive way of implementing latches, they create
testability problems when both the inputs of cross coupled NAND gates are ant
logic 1.
Add logic to make each cross-coupled
NAND/NOR gate behave like a buffer
during testing as shown below. When the
ScanMode signal is set to ‘1’ during test, the circuit converts the
cross-coupled gates into two inverters
If possible, it is better to implement
the latches using D-latches instead of cross-coupled SR latches. On the bottom
line, as latches reduce the test coverage, avoid inferring latches in the
design if possible.
6.
Fix Bi-Directional ports
One should fix the bi-directional ports
of the design. Ensure that the direction of Bi-directional ports are fixed to
either input or output by controlling the enable signal of the bi-directional
port. If the enable signal is generated internally, proper DFT logic has
to be employed. Or else, if the controlling signal is a primary port, provide
proper logic value on the bi-di controlling port during the test to make the
bi-di ports unidirectional.
If the primary DFT pads (scan enable,
scan-ins, scan-outs, scan-clks etc.) are bi-directional, fix them and make the
respective pads, uni-directional accordingly with the ScanMode signal.
For the pads, other than DFT ports, fix them using ScanEnable signal. This will
improve the test coverage.
Note: If Scan Mode it self is
bi-directional, be sure that the bi-di control pin is accessable to the ATE. So
that, one can make the ScanMode signal to input by providing the proper value
to the control pin during test.
If it is scan clock, scanenable,
scanmode, scan-in ports fix their direction to input. If scan-out ports are
bi-directional, fix their direction to output.
Following figure shows the fix for
scan-clock which is bi-directional with internally generated control logic.
7. Avoid contention due to non tri-state inputs (Wired Logic)
Wired-AND Wired-OR logics leads to
contention issues and should be avoided during the test. Most of the DFT tools
have the ability to perform contention ability checks on buses and wired logic.
When a net has more than one driving
object, wired-AND or wired-OR logic is introduced. A circuit re-modeling will
subsequently be performed where wired-ANDs are replaced by AND gates and
wire-ORs are replaced by OR gates.
8. Remove Redundant Logic and Test Point Addition
Remove Redundant Logic
This sounds un-reasonable. But still,
if the design is not properly optimized and left with some redundant logic, be
sure to optimize the logic properly. Most of the DFT tools will take care of
optimizing the design.
Test Point Addition:
After test patterns and test coverage
is generated by the ATPG tool, be sure to verify the pin-point locations where
controllability and/or observability are insufficient. Insert test points at
these locations when I/O pad limit is allowed and again rerun the ATPG for
better coverage
9. Provide proper time margin for DFT inserted design
To improve a circuit’s fault coverage,
one may have to add a DFT circuitry in the silicon.
If the designer does not leave room for
DFT insertion, the newly created design may violate timing constraints. Thus,
during the early design stage, it is important to leave, say
15%-20% timing margin for future DFT
insertion. It is strongly recommended to re-simulate the DFT inserted design before
submitting it to ATPG and layout
10. Floating Nets
Avoid floating nets in the design. This
may cause unwanted leakage currents that leads to power failures. So, it is
strongly recommended to verify for floating nets in the design before and after
the DFT insertion.
11. Avoid Latches
Latches cannot be scanned unless they
are converted to scan latches. Such a conversion creates an extremely large
area overhead. If the latches are part of an embedded memory, it is possible to
model all the latches together as a memory. Using a memory model can reduce the
difficulty of generating patterns for faults near the latches; however, special
tests are required for the latches.
When latches are not part of the
memory, a more general solution is to make the latches transparent during test
mode. This takes care of the problem of propagating fault effects through the
latches, but the faults on the enable logic of latches become completely
untestable, reducing fault coverage. The best solution is to avoid using
latches in designs as much as possible.
12. Try avoiding combinational feedback loops
What is a combinational loop?
It is a simple form of D-Latch.
Designs that contain
combinationalfeedback loops have inherent testability problems.
Combinationfeedback loops may introduce internal logic states to a design that
scan-storage elements cannot control.
ATPG tools have a few methods for
breaking combinational feedback loops. Some of these methods are less harmful
to fault coverage than others, but all of them result in some loss of coverage.
Therefore, you should avoid combinational feedback loops whenever possible.
Most ATPG tools inform users of all the combinational-feedback loops present in
a design. If you cannot avoid these feedback loops, then you should break the
feedback loop by inserting an additional flip-flop that is present in the
feedback path only during scan-test mode. This modification results in the
highest fault coverage. If you cannot insert a flip-flop, then insert a
multiplexer in the feedback path that drives a constant value during scan-test
mode. This approach results in lower coverage than the flip-flop option but
higher coverage than if you allow the tool to break the loop by assuming an
unknown value as a result of the
loop.
Combinational feedback loops introduce
sequential behavior into otherwise combinational logic, making it difficult to
use combinational ATPG tools. In addition, such loops may lead to races and
hazards, resulting in unpredictable circuit behavior. These loops are generally
delay-dependent and therefore can't be tested with any ATPG algorithm.
Typically, designers will omit
combinational feedback loops from their designs. However, the loops can be
created unknowingly when two portions of a design done by different designers
are tied together.
If creating combinational feedback
loops are unavoidable, designers should add test logic to the design. This fix
allows combinational feedback loops to be broken during testing by using a scan
flip-flop. One should break this loop during scan mode for the ATPG tool
to predict the operation of the circuit.
