Ques:----- Can any body tell me
1) What causes HOLD VIOLATIONS in DESIGN.
2) How it effects DESIGN.
3) What changes need to be done to make DESIGN work.
1) What causes HOLD VIOLATIONS in DESIGN.
2) How it effects DESIGN.
3) What changes need to be done to make DESIGN work.
Ans:----
Hi Friend,
1) What causes HOLD VIOLATIONS in DESIGN.
Simply, data should be hold for some time (hold time) after the edge of the clock. So, if the data changes with the hold time might cause violation. In general, hold time will be fixed during backend work (during PNR) while building clock tree. If u r a frontend designer, concentrate on fixing setup time violations rather than hold violations.
2) How it effects DESIGN.
If a chip is done with some setup violations it can work by reducing the frequency.
If achip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of the day. Hold vilations needs to be fixed.
3) What changes need to be done to make DESIGN work.
PNR tools will route and place the cells in such a way that no timing violations will occur. If still u face hold violations, u can manully work on it to fix. Manually place the cells to avoid hold violations, or in the worst case, u can keep some buffers in the datapath to avoid hold violations (but be sure setup timing is not effected.)
1) What causes HOLD VIOLATIONS in DESIGN.
Simply, data should be hold for some time (hold time) after the edge of the clock. So, if the data changes with the hold time might cause violation. In general, hold time will be fixed during backend work (during PNR) while building clock tree. If u r a frontend designer, concentrate on fixing setup time violations rather than hold violations.
2) How it effects DESIGN.
If a chip is done with some setup violations it can work by reducing the frequency.
If achip is done with hold violations, JUST DUMP the chip. This is how it effects at the end of the day. Hold vilations needs to be fixed.
3) What changes need to be done to make DESIGN work.
PNR tools will route and place the cells in such a way that no timing violations will occur. If still u face hold violations, u can manully work on it to fix. Manually place the cells to avoid hold violations, or in the worst case, u can keep some buffers in the datapath to avoid hold violations (but be sure setup timing is not effected.)
you said "If achip is done with hold violations, JUST DUMP the chip. "
>why can't reducing the frequency to settle the hold violation as setup violation ?
>could you explain it clearer ?
Equation for Setup Time
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter
Equation for Hold Time
Tclktoq + Tlogic - Tskew > Thold
Note that Hold Time equation is independent of clk frequency(i.e Time period Tclk)
key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout . ( But u can still test the current chip using Low supply voltage,
or High temperature or SS corner part that decrease hold time violation
>why can't reducing the frequency to settle the hold violation as setup violation ?
>could you explain it clearer ?
Equation for Setup Time
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter
Equation for Hold Time
Tclktoq + Tlogic - Tskew > Thold
Note that Hold Time equation is independent of clk frequency(i.e Time period Tclk)
key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout . ( But u can still test the current chip using Low supply voltage,
or High temperature or SS corner part that decrease hold time violation
Hi Friends,
Pls. make a note that HOLD violations are dangerous than SETUP. To keep it simple way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here.
T = Frequency of operation (can be variable)
Tcq = Flop clock to Flop output delay (fixed/constant)
Tcomb = Delay od the combinational logic between the Flops (can be variable)
Tsetup = Setup time of a Flop (fixed/constant)
Thold = Hold time of a Flop (fixed/constant)
Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable)
For SETUP,
T >= Tcq + Tcomb + Tsetup - Tskew
If you have setup time means u r violating the above rule. i.e some how the equation becomes
T < Tcq + Tcomb + Tsetup - Tskew
Now let us consider two cases.
Case1: During the Design development phase itself.
Now, you have three variables (T, Tcomb, Tskew.) to avoid the setup violation.
T : Reduce the frequency such that u saticify T >= Tcq + Tcomb + Tsetup - Tskew. But do u think it is the correct solution. Obviously, NO. This is because we have other options to avoid setup violations right.
Tcomb : If you reduce the combinational delay (between the Flops of violated path) such a way that T < Tcq + Tcomb + Tsetup - Tskew will become T >= Tcq + Tcomb + Tsetup - Tskew. So, the SETUP violation is avoided. How do u reduce the combinational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine.
Tskew: If u increase the skew, u can change T < Tcq + Tcomb + Tsetup - Tskew to T >= Tcq + Tcomb + Tsetup - Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing.
Case2: After the CHIP is manufatured and is in your hand.
In this case, one cannot access the Tcomb and Tskew. Only the variable that can handle is T.
So, Just reduce the frequency (T) such that the violated equation, T < Tcq + Tcomb + Tsetup - Tskew becomes violation free equation T >= Tcq + Tcomb + Tsetup - Tskew.
So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency.
For HOLD,
Thold + Tskew <= Tcq + Tcomb
If you have setup time means u r violating the above rule. i.e some how the equation becomes
Thold + Tskew > Tcq + Tcomb andur
Now let us consider two cases.
Case1: During the Design development phase itself.
You have two variables in hand (Tcomb, Tskew) to avoid HOLD violations.
Tcomb: Increase the Tcomb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew > Tcq + Tcomb to Thold + Tskew <= Tcq + Tcomb. But this might effect the SETUP time as you are increasing the delay of combinational path. So this may not be the perfect solution always.
Tskew : Reduce the clock skew so that you will land on Thold + Tskew <= Tcq + Tcomb. To reduce the clock skew, the best solution is to take the help of your PNR engineer.
Case2: After the CHIP is manufatured and is in your hand.
Do you see any variables that will fix the hold violations after manufaturing?????!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioning chips to the customers.
So becareful with the HOLD violations.
Note: One can get those equations if u put those scenarios on a paper and develop the timing diagrams.
Hope I've explained it properly.
Regards,
xxxxxx.
Hi xxxxx,
It is nice information. Could you please give us more information on
" u will need a new metal fix tapeout . ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease hold time violation)"
It may give us more information on this topic.
Thanks in advance.
Regards,
xxxxxxx
Pls. make a note that HOLD violations are dangerous than SETUP. To keep it simple way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here.
T = Frequency of operation (can be variable)
Tcq = Flop clock to Flop output delay (fixed/constant)
Tcomb = Delay od the combinational logic between the Flops (can be variable)
Tsetup = Setup time of a Flop (fixed/constant)
Thold = Hold time of a Flop (fixed/constant)
Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable)
For SETUP,
T >= Tcq + Tcomb + Tsetup - Tskew
If you have setup time means u r violating the above rule. i.e some how the equation becomes
T < Tcq + Tcomb + Tsetup - Tskew
Now let us consider two cases.
Case1: During the Design development phase itself.
Now, you have three variables (T, Tcomb, Tskew.) to avoid the setup violation.
T : Reduce the frequency such that u saticify T >= Tcq + Tcomb + Tsetup - Tskew. But do u think it is the correct solution. Obviously, NO. This is because we have other options to avoid setup violations right.
Tcomb : If you reduce the combinational delay (between the Flops of violated path) such a way that T < Tcq + Tcomb + Tsetup - Tskew will become T >= Tcq + Tcomb + Tsetup - Tskew. So, the SETUP violation is avoided. How do u reduce the combinational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine.
Tskew: If u increase the skew, u can change T < Tcq + Tcomb + Tsetup - Tskew to T >= Tcq + Tcomb + Tsetup - Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing.
Case2: After the CHIP is manufatured and is in your hand.
In this case, one cannot access the Tcomb and Tskew. Only the variable that can handle is T.
So, Just reduce the frequency (T) such that the violated equation, T < Tcq + Tcomb + Tsetup - Tskew becomes violation free equation T >= Tcq + Tcomb + Tsetup - Tskew.
So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency.
For HOLD,
Thold + Tskew <= Tcq + Tcomb
If you have setup time means u r violating the above rule. i.e some how the equation becomes
Thold + Tskew > Tcq + Tcomb and
Now let us consider two cases.
Case1: During the Design development phase itself.
You have two variables in hand (Tcomb, Tskew) to avoid HOLD violations.
Tcomb: Increase the Tcomb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew > Tcq + Tcomb to Thold + Tskew <= Tcq + Tcomb. But this might effect the SETUP time as you are increasing the delay of combinational path. So this may not be the perfect solution always.
Tskew : Reduce the clock skew so that you will land on Thold + Tskew <= Tcq + Tcomb. To reduce the clock skew, the best solution is to take the help of your PNR engineer.
Case2: After the CHIP is manufatured and is in your hand.
Do you see any variables that will fix the hold violations after manufaturing?????!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioning chips to the customers.
So becareful with the HOLD violations.
Note: One can get those equations if u put those scenarios on a paper and develop the timing diagrams.
Hope I've explained it properly.
Regards,
xxxxxx.
Hi xxxxx,
It is nice information. Could you please give us more information on
" u will need a new metal fix tapeout . ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease hold time violation)"
It may give us more information on this topic.
Thanks in advance.
Regards,
xxxxxxx
what i meant was , when u have hold time violation , u dont need to throw away chip and wait for 3 months for fixed chip to come back. in the meanwhile , by playing with voltage and temperature , u can do other functional tests on the chip . since normally hold time simulation are done at " FF corner , high voltage, low temperature " which is the pessimistic case for hold time , by decreasing voltage , using high temperature, and a SS corner chip , we may be lucky enough to find a part that works , to do other functional tests to catch any other bugs before next tapeout.
